X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Falpha%2Fkernel%2Fsys_dp264.c;h=85d2f933dd07b0b8d9ca88f13646e302d13e1328;hb=refs%2Fheads%2Fvserver;hp=307ce54aca384376b65bfb7d794aaea6e6ccadb5;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 307ce54ac..85d2f933d 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c @@ -12,19 +12,18 @@ * Code supporting the DP264 (EV6+TSUNAMI). */ -#include #include #include #include #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -43,7 +42,7 @@ static unsigned long cached_irq_mask; /* dp264 boards handle at max four CPUs */ static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL }; -spinlock_t dp264_irq_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(dp264_irq_lock); static void tsunami_update_irq_hw(unsigned long mask) @@ -53,7 +52,6 @@ tsunami_update_irq_hw(unsigned long mask) register int bcpu = boot_cpuid; #ifdef CONFIG_SMP - register unsigned long cpm = cpu_present_mask; volatile unsigned long *dim0, *dim1, *dim2, *dim3; unsigned long mask0, mask1, mask2, mask3, dummy; @@ -72,10 +70,10 @@ tsunami_update_irq_hw(unsigned long mask) dim1 = &cchip->dim1.csr; dim2 = &cchip->dim2.csr; dim3 = &cchip->dim3.csr; - if ((cpm & 1) == 0) dim0 = &dummy; - if ((cpm & 2) == 0) dim1 = &dummy; - if ((cpm & 4) == 0) dim2 = &dummy; - if ((cpm & 8) == 0) dim3 = &dummy; + if (!cpu_possible(0)) dim0 = &dummy; + if (!cpu_possible(1)) dim1 = &dummy; + if (!cpu_possible(2)) dim2 = &dummy; + if (!cpu_possible(3)) dim3 = &dummy; *dim0 = mask0; *dim1 = mask1; @@ -164,13 +162,13 @@ clipper_end_irq(unsigned int irq) } static void -cpu_set_irq_affinity(unsigned int irq, unsigned long affinity) +cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) { int cpu; for (cpu = 0; cpu < 4; cpu++) { unsigned long aff = cpu_irq_affinity[cpu]; - if (affinity & (1UL << cpu)) + if (cpu_isset(cpu, affinity)) aff |= 1UL << irq; else aff &= ~(1UL << irq); @@ -179,7 +177,7 @@ cpu_set_irq_affinity(unsigned int irq, unsigned long affinity) } static void -dp264_set_affinity(unsigned int irq, unsigned long affinity) +dp264_set_affinity(unsigned int irq, cpumask_t affinity) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(irq, affinity); @@ -188,7 +186,7 @@ dp264_set_affinity(unsigned int irq, unsigned long affinity) } static void -clipper_set_affinity(unsigned int irq, unsigned long affinity) +clipper_set_affinity(unsigned int irq, cpumask_t affinity) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(irq - 16, affinity); @@ -219,7 +217,7 @@ static struct hw_interrupt_type clipper_irq_type = { }; static void -dp264_device_interrupt(unsigned long vector, struct pt_regs * regs) +dp264_device_interrupt(unsigned long vector) { #if 1 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!! \n"); @@ -238,9 +236,9 @@ dp264_device_interrupt(unsigned long vector, struct pt_regs * regs) i = ffz(~pld); pld &= pld - 1; /* clear least bit set */ if (i == 55) - isa_device_interrupt(vector, regs); + isa_device_interrupt(vector); else - handle_irq(16 + i, 16 + i, regs); + handle_irq(16 + i); #if 0 TSUNAMI_cchip->dir0.csr = 1UL << i; mb(); tmp = TSUNAMI_cchip->dir0.csr; @@ -250,7 +248,7 @@ dp264_device_interrupt(unsigned long vector, struct pt_regs * regs) } static void -dp264_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) +dp264_srm_device_interrupt(unsigned long vector) { int irq; @@ -270,11 +268,11 @@ dp264_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) if (irq >= 32) irq -= 16; - handle_irq(irq, regs); + handle_irq(irq); } static void -clipper_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) +clipper_srm_device_interrupt(unsigned long vector) { int irq; @@ -292,7 +290,7 @@ clipper_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) * * Eg IRQ 24 is DRIR bit 8, etc, etc */ - handle_irq(irq, regs); + handle_irq(irq); } static void __init @@ -301,7 +299,7 @@ init_tsunami_irqs(struct hw_interrupt_type * ops, int imin, int imax) long i; for (i = imin; i <= imax; ++i) { irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].handler = ops; + irq_desc[i].chip = ops; } } @@ -395,6 +393,22 @@ clipper_init_irq(void) * 10 64 bit PCI option slot 3 (not bus 0) */ +static int __init +isa_irq_fixup(struct pci_dev *dev, int irq) +{ + u8 irq8; + + if (irq > 0) + return irq; + + /* This interrupt is routed via ISA bridge, so we'll + just have to trust whatever value the console might + have assigned. */ + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8); + + return irq8 & 0xf; +} + static int __init dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { @@ -408,25 +422,13 @@ dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */ }; const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5; - struct pci_controller *hose = dev->sysdata; int irq = COMMON_TABLE_LOOKUP; - if (irq > 0) { + if (irq > 0) irq += 16 * hose->index; - } else { - /* ??? The Contaq IDE controller on the ISA bridge uses - "legacy" interrupts 14 and 15. I don't know if anything - can wind up at the same slot+pin on hose1, so we'll - just have to trust whatever value the console might - have assigned. */ - - u8 irq8; - pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8); - irq = irq8; - } - return irq; + return isa_irq_fixup(dev, irq); } static int __init @@ -454,7 +456,8 @@ monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/ }; const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5; - return COMMON_TABLE_LOOKUP; + + return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); } static u8 __init @@ -508,7 +511,8 @@ webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */ }; const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5; - return COMMON_TABLE_LOOKUP; + + return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); } static int __init @@ -525,14 +529,13 @@ clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */ }; const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5; - struct pci_controller *hose = dev->sysdata; int irq = COMMON_TABLE_LOOKUP; if (irq > 0) irq += 16 * hose->index; - return irq; + return isa_irq_fixup(dev, irq); } static void __init @@ -570,7 +573,6 @@ struct alpha_machine_vector dp264_mv __initmv = { DO_EV6_MMU, DO_DEFAULT_RTC, DO_TSUNAMI_IO, - DO_TSUNAMI_BUS, .machine_check = tsunami_machine_check, .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, .min_io_address = DEFAULT_IO_BASE, @@ -595,7 +597,6 @@ struct alpha_machine_vector monet_mv __initmv = { DO_EV6_MMU, DO_DEFAULT_RTC, DO_TSUNAMI_IO, - DO_TSUNAMI_BUS, .machine_check = tsunami_machine_check, .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, .min_io_address = DEFAULT_IO_BASE, @@ -619,7 +620,6 @@ struct alpha_machine_vector webbrick_mv __initmv = { DO_EV6_MMU, DO_DEFAULT_RTC, DO_TSUNAMI_IO, - DO_TSUNAMI_BUS, .machine_check = tsunami_machine_check, .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, .min_io_address = DEFAULT_IO_BASE, @@ -643,7 +643,6 @@ struct alpha_machine_vector clipper_mv __initmv = { DO_EV6_MMU, DO_DEFAULT_RTC, DO_TSUNAMI_IO, - DO_TSUNAMI_BUS, .machine_check = tsunami_machine_check, .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, .min_io_address = DEFAULT_IO_BASE, @@ -672,7 +671,6 @@ struct alpha_machine_vector shark_mv __initmv = { DO_EV6_MMU, DO_DEFAULT_RTC, DO_TSUNAMI_IO, - DO_TSUNAMI_BUS, .machine_check = tsunami_machine_check, .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, .min_io_address = DEFAULT_IO_BASE,