X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Falpha%2Fkernel%2Fsys_ruffian.c;h=5b99cf3cd69cb3be72cf733d10f14885feb74f66;hb=refs%2Fheads%2Fvserver;hp=3438b8d4880d9f160773c1857c62de4f754dab2a;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/alpha/kernel/sys_ruffian.c b/arch/alpha/kernel/sys_ruffian.c index 3438b8d48..5b99cf3cd 100644 --- a/arch/alpha/kernel/sys_ruffian.c +++ b/arch/alpha/kernel/sys_ruffian.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "proto.h" #include "irq_impl.h" @@ -64,6 +65,8 @@ ruffian_init_irq(void) common_init_isa_dma(); } +#define RUFFIAN_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) + static void __init ruffian_init_rtc(void) { @@ -72,8 +75,8 @@ ruffian_init_rtc(void) /* Setup interval timer. */ outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */ - outb(LATCH & 0xff, 0x40); /* LSB */ - outb(LATCH >> 8, 0x40); /* MSB */ + outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */ + outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */ outb(0xb6, 0x43); /* pit counter 2: speaker */ outb(0x31, 0x42); @@ -179,16 +182,16 @@ static unsigned long __init ruffian_get_bank_size(unsigned long offset) { unsigned long bank_addr, bank, ret = 0; - + /* Valid offsets are: 0x800, 0x840 and 0x880 since Ruffian only uses three banks. */ bank_addr = (unsigned long)PYXIS_MCR + offset; bank = *(vulp)bank_addr; - + /* Check BANK_ENABLE */ if (bank & 0x01) { static unsigned long size[] __initdata = { - 0x40000000UL, /* 0x00, 1G */ + 0x40000000UL, /* 0x00, 1G */ 0x20000000UL, /* 0x02, 512M */ 0x10000000UL, /* 0x04, 256M */ 0x08000000UL, /* 0x06, 128M */ @@ -200,7 +203,7 @@ ruffian_get_bank_size(unsigned long offset) }; bank = (bank & 0x1e) >> 1; - if (bank < sizeof(size)/sizeof(*size)) + if (bank < ARRAY_SIZE(size)) ret = size[bank]; } @@ -217,7 +220,6 @@ struct alpha_machine_vector ruffian_mv __initmv = { DO_EV5_MMU, DO_DEFAULT_RTC, DO_PYXIS_IO, - DO_CIA_BUS, .machine_check = cia_machine_check, .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS, .min_io_address = DEFAULT_IO_BASE,