X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fcommon%2Fvic.c;fp=arch%2Farm%2Fcommon%2Fvic.c;h=a45ed1687a591eb27c5db61af904d0280446feb9;hb=64ba3f394c830ec48a1c31b53dcae312c56f1604;hp=43d278134521a23f7d5ab9e9075d3de0e9ab6efb;hpb=be1e6109ac94a859551f8e1774eb9a8469fe055c;p=linux-2.6.git

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 43d278134..a45ed1687 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -22,73 +22,67 @@
 #include <linux/list.h>
 
 #include <asm/io.h>
+#include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
+static void __iomem *vic_base;
+
 static void vic_mask_irq(unsigned int irq)
 {
-	void __iomem *base = get_irq_chipdata(irq);
-	irq &= 31;
-	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+	irq -= IRQ_VIC_START;
+	writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
 }
 
 static void vic_unmask_irq(unsigned int irq)
 {
-	void __iomem *base = get_irq_chipdata(irq);
-	irq &= 31;
-	writel(1 << irq, base + VIC_INT_ENABLE);
+	irq -= IRQ_VIC_START;
+	writel(1 << irq, vic_base + VIC_INT_ENABLE);
 }
 
-static struct irq_chip vic_chip = {
-	.name	= "VIC",
+static struct irqchip vic_chip = {
 	.ack	= vic_mask_irq,
 	.mask	= vic_mask_irq,
 	.unmask	= vic_unmask_irq,
 };
 
-/**
- * vic_init - initialise a vectored interrupt controller
- * @base: iomem base address
- * @irq_start: starting interrupt number, must be muliple of 32
- * @vic_sources: bitmask of interrupt sources to allow
- */
-void __init vic_init(void __iomem *base, unsigned int irq_start,
-		     u32 vic_sources)
+void __init vic_init(void __iomem *base, u32 vic_sources)
 {
 	unsigned int i;
 
+	vic_base = base;
+
 	/* Disable all interrupts initially. */
 
-	writel(0, base + VIC_INT_SELECT);
-	writel(0, base + VIC_INT_ENABLE);
-	writel(~0, base + VIC_INT_ENABLE_CLEAR);
-	writel(0, base + VIC_IRQ_STATUS);
-	writel(0, base + VIC_ITCR);
-	writel(~0, base + VIC_INT_SOFT_CLEAR);
+	writel(0, vic_base + VIC_INT_SELECT);
+	writel(0, vic_base + VIC_INT_ENABLE);
+	writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
+	writel(0, vic_base + VIC_IRQ_STATUS);
+	writel(0, vic_base + VIC_ITCR);
+	writel(~0, vic_base + VIC_INT_SOFT_CLEAR);
 
 	/*
 	 * Make sure we clear all existing interrupts
 	 */
-	writel(0, base + VIC_VECT_ADDR);
+	writel(0, vic_base + VIC_VECT_ADDR);
 	for (i = 0; i < 19; i++) {
 		unsigned int value;
 
-		value = readl(base + VIC_VECT_ADDR);
-		writel(value, base + VIC_VECT_ADDR);
+		value = readl(vic_base + VIC_VECT_ADDR);
+		writel(value, vic_base + VIC_VECT_ADDR);
 	}
 
 	for (i = 0; i < 16; i++) {
-		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+		void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4);
 		writel(VIC_VECT_CNTL_ENABLE | i, reg);
 	}
 
-	writel(32, base + VIC_DEF_VECT_ADDR);
+	writel(32, vic_base + VIC_DEF_VECT_ADDR);
 
 	for (i = 0; i < 32; i++) {
-		unsigned int irq = irq_start + i;
+		unsigned int irq = IRQ_VIC_START + i;
 
 		set_irq_chip(irq, &vic_chip);
-		set_irq_chipdata(irq, base);
 
 		if (vic_sources & (1 << i)) {
 			set_irq_handler(irq, do_level_IRQ);