X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fkernel%2Fhead.S;h=cf495a3084b31f8a7ead7089508ff16096864ae9;hb=refs%2Fheads%2Fvserver;hp=4de9941c54e27777c85ba11f6db0299f03ad57b8;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 4de9941c5..cf495a308 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -1,7 +1,9 @@ /* - * linux/arch/arm/kernel/head-armv.S + * linux/arch/arm/kernel/head.S * * Copyright (C) 1994-2002 Russell King + * Copyright (c) 2003 ARM Limited + * All Rights Reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -9,48 +11,47 @@ * * Kernel startup code for all 32-bit CPUs */ -#include #include #include #include -#include -#include +#include #include -#include +#include +#include +#include +#include + +#if (PHYS_OFFSET & 0x001fffff) +#error "PHYS_OFFSET must be at an even 2MiB boundary!" +#endif + +#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) +#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) /* - * We place the page tables 16K below TEXTADDR. Therefore, we must make sure - * that TEXTADDR is correctly set. Currently, we expect the least significant - * 16 bits to be 0x8000, but we could probably relax this restriction to - * TEXTADDR > PAGE_OFFSET + 0x4000 - * - * Note that swapper_pg_dir is the virtual address of the page tables, and - * pgtbl gives us a position-independent reference to these tables. We can - * do this because stext == TEXTADDR - * - * swapper_pg_dir, pgtbl and krnladr are all closely related. + * swapper_pg_dir is the virtual address of the initial page table. + * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must + * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect + * the least significant 16 bits to be 0x8000, but we could probably + * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. */ -#if (TEXTADDR & 0xffff) != 0x8000 -#error TEXTADDR must start at 0xXXXX8000 +#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 +#error KERNEL_RAM_VADDR must start at 0xXXXX8000 #endif .globl swapper_pg_dir - .equ swapper_pg_dir, TEXTADDR - 0x4000 + .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 - .macro pgtbl, reg - adr \reg, stext - sub \reg, \reg, #0x4000 + .macro pgtbl, rd + ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) .endm -/* - * Since the page table is closely related to the kernel start address, we - * can convert the page table base address to the base address of the section - * containing both. - */ - .macro krnladr, rd, pgtable - bic \rd, \pgtable, #0x000ff000 - .endm +#ifdef CONFIG_XIP_KERNEL +#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) +#else +#define TEXTADDR KERNEL_RAM_VADDR +#endif /* * Kernel startup entry point. @@ -71,83 +72,125 @@ * circumstances, zImage) is for. */ __INIT - .type stext, #function + .type stext, %function ENTRY(stext) - mov r12, r0 - mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ make sure svc mode - msr cpsr_c, r0 @ and all irqs disabled - bl __lookup_processor_type - teq r10, #0 @ invalid processor? - moveq r0, #'p' @ yes, error 'p' - beq __error - bl __lookup_architecture_type - teq r7, #0 @ invalid architecture? - moveq r0, #'a' @ yes, error 'a' - beq __error + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode + @ and irqs disabled + mrc p15, 0, r9, c0, c0 @ get processor id + bl __lookup_processor_type @ r5=procinfo r9=cpuid + movs r10, r5 @ invalid processor (r5=0)? + beq __error_p @ yes, error 'p' + bl __lookup_machine_type @ r5=machinfo + movs r8, r5 @ invalid machine (r5=0)? + beq __error_a @ yes, error 'a' bl __create_page_tables /* * The following calls CPU specific code in a position independent * manner. See arch/arm/mm/proc-*.S for details. r10 = base of - * xxx_proc_info structure selected by __lookup_architecture_type + * xxx_proc_info structure selected by __lookup_machine_type * above. On return, the CPU will be ready for the MMU to be * turned on, and r0 will hold the CPU control register value. */ - adr lr, __turn_mmu_on @ return (PIC) address - add pc, r10, #12 + ldr r13, __switch_data @ address to jump to after + @ mmu has been enabled + adr lr, __enable_mmu @ return (PIC) address + add pc, r10, #PROCINFO_INITFUNC + +#if defined(CONFIG_SMP) + .type secondary_startup, #function +ENTRY(secondary_startup) + /* + * Common entry point for secondary CPUs. + * + * Ensure that we're in SVC mode, and IRQs are disabled. Lookup + * the processor type - there is no need to check the machine type + * as it has already been validated by the primary processor. + */ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + mrc p15, 0, r9, c0, c0 @ get processor id + bl __lookup_processor_type + movs r10, r5 @ invalid processor? + moveq r0, #'p' @ yes, error 'p' + beq __error + + /* + * Use the page tables supplied from __cpu_up. + */ + adr r4, __secondary_data + ldmia r4, {r5, r7, r13} @ address to jump to after + sub r4, r4, r5 @ mmu has been enabled + ldr r4, [r7, r4] @ get secondary_data.pgdir + adr lr, __enable_mmu @ return address + add pc, r10, #PROCINFO_INITFUNC @ initialise processor + @ (return control reg) + + /* + * r6 = &secondary_data + */ +ENTRY(__secondary_switched) + ldr sp, [r7, #4] @ get secondary_data.stack + mov fp, #0 + b secondary_start_kernel + + .type __secondary_data, %object +__secondary_data: + .long . + .long secondary_data + .long __secondary_switched +#endif /* defined(CONFIG_SMP) */ + - .type __switch_data, %object -__switch_data: - .long __mmap_switched - .long __bss_start @ r4 - .long _end @ r5 - .long processor_id @ r6 - .long __machine_arch_type @ r7 - .long cr_alignment @ r8 - .long init_thread_union+8192 @ sp + +/* + * Setup common bits before finally enabling the MMU. Essentially + * this is just loading the page table pointer and domain access + * registers. + */ + .type __enable_mmu, %function +__enable_mmu: +#ifdef CONFIG_ALIGNMENT_TRAP + orr r0, r0, #CR_A +#else + bic r0, r0, #CR_A +#endif +#ifdef CONFIG_CPU_DCACHE_DISABLE + bic r0, r0, #CR_C +#endif +#ifdef CONFIG_CPU_BPREDICT_DISABLE + bic r0, r0, #CR_Z +#endif +#ifdef CONFIG_CPU_ICACHE_DISABLE + bic r0, r0, #CR_I +#endif + mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT)) + mcr p15, 0, r5, c3, c0, 0 @ load domain access register + mcr p15, 0, r4, c2, c0, 0 @ load page table pointer + b __turn_mmu_on /* * Enable the MMU. This completely changes the structure of the visible * memory space. You will not be able to trace execution through this. * If you have an enquiry about this, *please* check the linux-arm-kernel * mailing list archives BEFORE sending another post to the list. + * + * r0 = cp#15 control register + * r13 = *virtual* address to jump to upon completion + * + * other registers depend on the function called upon completion */ .align 5 .type __turn_mmu_on, %function __turn_mmu_on: - ldr lr, __switch_data -#ifdef CONFIG_ALIGNMENT_TRAP - orr r0, r0, #2 @ ...........A. -#endif + mov r0, r0 mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg mov r3, r3 mov r3, r3 - mov pc, lr - -/* - * The following fragment of code is executed with the MMU on, and uses - * absolute addresses; this is not position independent. - * - * r0 = processor control register - * r1 = machine ID - * r9 = processor ID - * r12 = value of r0 when kernel was called (currently always zero) - */ - .align 5 -__mmap_switched: - adr r3, __switch_data + 4 - ldmia r3, {r4, r5, r6, r7, r8, sp} - mov fp, #0 @ Clear BSS (and zero fp) -1: cmp r4, r5 - strcc fp, [r4],#4 - bcc 1b - str r9, [r6] @ Save processor ID - str r1, [r7] @ Save machine type - bic r2, r0, #2 @ Clear 'A' bit - stmia r8, {r0, r2} @ Save control register values - b start_kernel - + mov pc, r13 @@ -156,14 +199,15 @@ __mmap_switched: * amount which are required to get the kernel running, which * generally means mapping in the kernel code. * - * We only map in 4MB of RAM, which should be sufficient in - * all cases. + * r8 = machinfo + * r9 = cpuid + * r10 = procinfo * - * r5 = physical address of start of RAM - * r6 = physical IO address - * r7 = byte offset into page tables for IO - * r8 = page table flags + * Returns: + * r0, r3, r6, r7 corrupted + * r4 = physical page table address */ + .type __create_page_tables, %function __create_page_tables: pgtbl r4 @ page table address @@ -172,74 +216,92 @@ __create_page_tables: */ mov r0, r4 mov r3, #0 - add r2, r0, #0x4000 + add r6, r0, #0x4000 1: str r3, [r0], #4 str r3, [r0], #4 str r3, [r0], #4 str r3, [r0], #4 - teq r0, r2 + teq r0, r6 bne 1b + ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags + /* * Create identity mapping for first MB of kernel to * cater for the MMU enable. This identity mapping - * will be removed by paging_init() + * will be removed by paging_init(). We use our current program + * counter to determine corresponding section base address. */ - krnladr r2, r4 @ start of kernel - add r3, r8, r2 @ flags + kernel base - str r3, [r4, r2, lsr #18] @ identity mapping + mov r6, pc, lsr #20 @ start of kernel section + orr r3, r7, r6, lsl #20 @ flags + kernel base + str r3, [r4, r6, lsl #2] @ identity mapping /* * Now setup the pagetables for our kernel direct - * mapped region. We round TEXTADDR down to the - * nearest megabyte boundary. + * mapped region. */ - add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel - bic r2, r3, #0x00f00000 - str r2, [r0] @ PAGE_OFFSET + 0MB - add r0, r0, #(TEXTADDR & 0x00f00000) >> 18 - str r3, [r0], #4 @ KERNEL + 0MB - add r3, r3, #1 << 20 - str r3, [r0], #4 @ KERNEL + 1MB - add r3, r3, #1 << 20 - str r3, [r0], #4 @ KERNEL + 2MB - add r3, r3, #1 << 20 - str r3, [r0], #4 @ KERNEL + 3MB + add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel + str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]! + + ldr r6, =(_end - PAGE_OFFSET - 1) @ r6 = number of sections + mov r6, r6, lsr #20 @ needed for kernel minus 1 + +1: add r3, r3, #1 << 20 + str r3, [r0, #4]! + subs r6, r6, #1 + bgt 1b + + /* + * Then map first 1MB of ram in case it contains our boot params. + */ + add r0, r4, #PAGE_OFFSET >> 18 + orr r6, r7, #(PHYS_OFFSET & 0xff000000) + orr r6, r6, #(PHYS_OFFSET & 0x00e00000) + str r6, [r0] + +#ifdef CONFIG_XIP_KERNEL + /* + * Map some ram to cover our .data and .bss areas. + * Mapping 3MB should be plenty. + */ + sub r3, r4, #PHYS_OFFSET + mov r3, r3, lsr #20 + add r0, r0, r3, lsl #2 + add r6, r6, r3, lsl #20 + str r6, [r0], #4 + add r6, r6, #(1 << 20) + str r6, [r0], #4 + add r6, r6, #(1 << 20) + str r6, [r0] +#endif - bic r8, r8, #0x0c @ turn off cacheable - @ and bufferable bits #ifdef CONFIG_DEBUG_LL + ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags /* * Map in IO space for serial debugging. * This allows debug messages to be output * via a serial console before paging_init. */ - add r0, r4, r7 - rsb r3, r7, #0x4000 @ PTRS_PER_PGD*sizeof(long) - cmp r3, #0x0800 - addge r2, r0, #0x0800 - addlt r2, r0, r3 - orr r3, r6, r8 + ldr r3, [r8, #MACHINFO_PGOFFIO] + add r0, r4, r3 + rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) + cmp r3, #0x0800 @ limit to 512MB + movhi r3, #0x0800 + add r6, r0, r3 + ldr r3, [r8, #MACHINFO_PHYSIO] + orr r3, r3, r7 1: str r3, [r0], #4 add r3, r3, #1 << 20 - teq r0, r2 + teq r0, r6 bne 1b #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) /* - * If we're using the NetWinder, we need to map in - * the 16550-type serial port for the debug messages + * If we're using the NetWinder or CATS, we also need to map + * in the 16550-type serial port for the debug messages */ - teq r1, #MACH_TYPE_NETWINDER - teqne r1, #MACH_TYPE_CATS - bne 1f - add r0, r4, #0x3fc0 @ ff000000 - mov r3, #0x7c000000 - orr r3, r3, r8 - str r3, [r0], #4 - add r3, r3, #1 << 20 - str r3, [r0], #4 -1: -#endif + add r0, r4, #0xff000000 >> 18 + orr r3, r7, #0x7c000000 + str r3, [r0] #endif #ifdef CONFIG_ARCH_RPC /* @@ -247,125 +309,14 @@ __create_page_tables: * Similar reasons here - for debug. This is * only for Acorn RiscPC architectures. */ - add r0, r4, #0x80 @ 02000000 - mov r3, #0x02000000 - orr r3, r3, r8 + add r0, r4, #0x02000000 >> 18 + orr r3, r7, #0x02000000 str r3, [r0] - add r0, r4, #0x3600 @ d8000000 + add r0, r4, #0xd8000000 >> 18 str r3, [r0] #endif - mov pc, lr - - - -/* - * Exception handling. Something went wrong and we can't proceed. We - * ought to tell the user, but since we don't have any guarantee that - * we're even running on the right architecture, we do virtually nothing. - * - * r0 = ascii error character: - * a = invalid architecture - * p = invalid processor - * i = invalid calling convention - * - * Generally, only serious errors cause this. - */ -__error: -#ifdef CONFIG_DEBUG_LL - mov r8, r0 @ preserve r0 - adr r0, err_str - bl printascii - mov r0, r8 - bl printch #endif -#ifdef CONFIG_ARCH_RPC -/* - * Turn the screen red on a error - RiscPC only. - */ - mov r0, #0x02000000 - mov r3, #0x11 - orr r3, r3, r3, lsl #8 - orr r3, r3, r3, lsl #16 - str r3, [r0], #4 - str r3, [r0], #4 - str r3, [r0], #4 - str r3, [r0], #4 -#endif -1: mov r0, r0 - b 1b - -#ifdef CONFIG_DEBUG_LL -err_str: - .asciz "\nError: " - .align -#endif - -/* - * Read processor ID register (CP#15, CR0), and look up in the linker-built - * supported processor list. Note that we can't use the absolute addresses - * for the __proc_info lists since we aren't running with the MMU on - * (and therefore, we are not in the correct address space). We have to - * calculate the offset. - * - * Returns: - * r5, r6, r7 corrupted - * r8 = page table flags - * r9 = processor ID - * r10 = pointer to processor structure - */ -__lookup_processor_type: - adr r5, 2f - ldmia r5, {r7, r9, r10} - sub r5, r5, r10 @ convert addresses - add r7, r7, r5 @ to our address space - add r10, r9, r5 - mrc p15, 0, r9, c0, c0 @ get processor id -1: ldmia r10, {r5, r6, r8} @ value, mask, mmuflags - and r6, r6, r9 @ mask wanted bits - teq r5, r6 - moveq pc, lr - add r10, r10, #PROC_INFO_SZ @ sizeof(proc_info_list) - cmp r10, r7 - blt 1b - mov r10, #0 @ unknown processor mov pc, lr + .ltorg -/* - * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for - * more information about the __proc_info and __arch_info structures. - */ -2: .long __proc_info_end - .long __proc_info_begin - .long 2b - .long __arch_info_begin - .long __arch_info_end - -/* - * Lookup machine architecture in the linker-build list of architectures. - * Note that we can't use the absolute addresses for the __arch_info - * lists since we aren't running with the MMU on (and therefore, we are - * not in the correct address space). We have to calculate the offset. - * - * r1 = machine architecture number - * Returns: - * r2, r3, r4 corrupted - * r5 = physical start address of RAM - * r6 = physical address of IO - * r7 = byte offset into page tables for IO - */ -__lookup_architecture_type: - adr r4, 2b - ldmia r4, {r2, r3, r5, r6, r7} @ throw away r2, r3 - sub r5, r4, r5 @ convert addresses - add r4, r6, r5 @ to our address space - add r7, r7, r5 -1: ldr r5, [r4] @ get machine type - teq r5, r1 @ matches loader number? - beq 2f @ found - add r4, r4, #SIZEOF_MACHINE_DESC @ next machine_desc - cmp r4, r7 - blt 1b - mov r7, #0 @ unknown architecture - mov pc, lr -2: ldmib r4, {r5, r6, r7} @ found, get results - mov pc, lr +#include "head-common.S"