X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmach-ebsa110%2Fio.c;h=db38afb2aa884b2841ec8399aed50aa549ea089e;hb=refs%2Fheads%2Fvserver;hp=c948ddf30ed222b2d65120dc7870d9e166f5e240;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c index c948ddf30..db38afb2a 100644 --- a/arch/arm/mach-ebsa110/io.c +++ b/arch/arm/mach-ebsa110/io.c @@ -24,12 +24,13 @@ #include #include +#include #include #include -static u32 __isamem_convert_addr(void *addr) +static void __iomem *__isamem_convert_addr(const volatile void __iomem *addr) { - u32 ret, a = (u32) addr; + u32 ret, a = (u32 __force) addr; /* * The PCMCIA controller is wired up as follows: @@ -53,45 +54,47 @@ static u32 __isamem_convert_addr(void *addr) ret += 0xe8000000; if ((a & 0x20000) == (a & 0x40000) >> 1) - return ret; + return (void __iomem *)ret; BUG(); - return 0; + return NULL; } /* * read[bwl] and write[bwl] */ -u8 __readb(void *addr) +u8 __readb(const volatile void __iomem *addr) { - u32 ret, a = __isamem_convert_addr(addr); + void __iomem *a = __isamem_convert_addr(addr); + u32 ret; - if ((int)addr & 1) - ret = __raw_getl(a); + if ((unsigned long)addr & 1) + ret = __raw_readl(a); else - ret = __raw_getb(a); + ret = __raw_readb(a); return ret; } -u16 __readw(void *addr) +u16 __readw(const volatile void __iomem *addr) { - u32 a = __isamem_convert_addr(addr); + void __iomem *a = __isamem_convert_addr(addr); - if ((int)addr & 1) + if ((unsigned long)addr & 1) BUG(); - return __raw_getw(a); + return __raw_readw(a); } -u32 __readl(void *addr) +u32 __readl(const volatile void __iomem *addr) { - u32 ret, a = __isamem_convert_addr(addr); + void __iomem *a = __isamem_convert_addr(addr); + u32 ret; - if ((int)addr & 3) + if ((unsigned long)addr & 3) BUG(); - ret = __raw_getw(a); - ret |= __raw_getw(a + 4) << 16; + ret = __raw_readw(a); + ret |= __raw_readw(a + 4) << 16; return ret; } @@ -99,35 +102,35 @@ EXPORT_SYMBOL(__readb); EXPORT_SYMBOL(__readw); EXPORT_SYMBOL(__readl); -void __writeb(u8 val, void *addr) +void __writeb(u8 val, void __iomem *addr) { - u32 a = __isamem_convert_addr(addr); + void __iomem *a = __isamem_convert_addr(addr); - if ((int)addr & 1) - __raw_putl(val, a); + if ((unsigned long)addr & 1) + __raw_writel(val, a); else - __raw_putb(val, a); + __raw_writeb(val, a); } -void __writew(u16 val, void *addr) +void __writew(u16 val, void __iomem *addr) { - u32 a = __isamem_convert_addr(addr); + void __iomem *a = __isamem_convert_addr(addr); - if ((int)addr & 1) + if ((unsigned long)addr & 1) BUG(); - __raw_putw(val, a); + __raw_writew(val, a); } -void __writel(u32 val, void *addr) +void __writel(u32 val, void __iomem *addr) { - u32 a = __isamem_convert_addr(addr); + void __iomem *a = __isamem_convert_addr(addr); - if ((int)addr & 3) + if ((unsigned long)addr & 3) BUG(); - __raw_putw(val, a); - __raw_putw(val >> 16, a + 4); + __raw_writew(val, a); + __raw_writew(val >> 16, a + 4); } EXPORT_SYMBOL(__writeb); @@ -139,7 +142,11 @@ EXPORT_SYMBOL(__writel); ((p) >> 3) == (0x2f8 >> 3) || \ ((p) >> 3) == (0x378 >> 3)) -u8 __inb(int port) +/* + * We're addressing an 8 or 16-bit peripheral which tranfers + * odd addresses on the low ISA byte lane. + */ +u8 __inb8(unsigned int port) { u32 ret; @@ -147,108 +154,137 @@ u8 __inb(int port) * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - ret = __raw_getb(ISAIO_BASE + (port << 2)); + ret = __raw_readb((void __iomem *)ISAIO_BASE + (port << 2)); else { - u32 a = ISAIO_BASE + ((port & ~1) << 1); + void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); /* * Shame nothing else does */ if (port & 1) - ret = __raw_getl(a); + ret = __raw_readl(a); else - ret = __raw_getb(a); + ret = __raw_readb(a); } return ret; } -u16 __inw(int port) +/* + * We're addressing a 16-bit peripheral which transfers odd + * addresses on the high ISA byte lane. + */ +u8 __inb16(unsigned int port) { - u32 ret; + unsigned int offset; /* * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - ret = __raw_getw(ISAIO_BASE + (port << 2)); - else { - u32 a = ISAIO_BASE + ((port & ~1) << 1); + offset = port << 2; + else + offset = (port & ~1) << 1 | (port & 1); - /* - * Shame nothing else does - */ - if (port & 1) - BUG(); + return __raw_readb((void __iomem *)ISAIO_BASE + offset); +} + +u16 __inw(unsigned int port) +{ + unsigned int offset; - ret = __raw_getw(a); + /* + * The SuperIO registers use sane addressing techniques... + */ + if (SUPERIO_PORT(port)) + offset = port << 2; + else { + offset = port << 1; + BUG_ON(port & 1); } - return ret; + return __raw_readw((void __iomem *)ISAIO_BASE + offset); } -u32 __inl(int port) +/* + * Fake a 32-bit read with two 16-bit reads. Needed for 3c589. + */ +u32 __inl(unsigned int port) { - BUG(); - return 0; + void __iomem *a; + + if (SUPERIO_PORT(port) || port & 3) + BUG(); + + a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); + + return __raw_readw(a) | __raw_readw(a + 4) << 16; } -EXPORT_SYMBOL(__inb); +EXPORT_SYMBOL(__inb8); +EXPORT_SYMBOL(__inb16); EXPORT_SYMBOL(__inw); EXPORT_SYMBOL(__inl); -void __outb(u8 val, int port) +void __outb8(u8 val, unsigned int port) { /* * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - __raw_putb(val, ISAIO_BASE + (port << 2)); + __raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2)); else { - u32 a = ISAIO_BASE + ((port & ~1) << 1); + void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); /* * Shame nothing else does */ if (port & 1) - __raw_putl(val, a); + __raw_writel(val, a); else - __raw_putb(val, a); + __raw_writeb(val, a); } } -void __outw(u16 val, int port) +void __outb16(u8 val, unsigned int port) { - u32 off; + unsigned int offset; /* * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - off = port << 2; - else { - off = (port & ~1) << 1; - if (port & 1) - BUG(); + offset = port << 2; + else + offset = (port & ~1) << 1 | (port & 1); + + __raw_writeb(val, (void __iomem *)ISAIO_BASE + offset); +} +void __outw(u16 val, unsigned int port) +{ + unsigned int offset; + + /* + * The SuperIO registers use sane addressing techniques... + */ + if (SUPERIO_PORT(port)) + offset = port << 2; + else { + offset = port << 1; + BUG_ON(port & 1); } - __raw_putw(val, ISAIO_BASE + off); + __raw_writew(val, (void __iomem *)ISAIO_BASE + offset); } -void __outl(u32 val, int port) +void __outl(u32 val, unsigned int port) { BUG(); } -EXPORT_SYMBOL(__outb); +EXPORT_SYMBOL(__outb8); +EXPORT_SYMBOL(__outb16); EXPORT_SYMBOL(__outw); EXPORT_SYMBOL(__outl); -extern void __arch_writesb(unsigned long virt, const void *from, int len); -extern void __arch_writesw(unsigned long virt, const void *from, int len); -extern void __arch_writesl(unsigned long virt, const void *from, int len); -extern void __arch_readsb(unsigned long virt, void *from, int len); -extern void __arch_readsw(unsigned long virt, void *from, int len); -extern void __arch_readsl(unsigned long virt, void *from, int len); - void outsb(unsigned int port, const void *from, int len) { u32 off; @@ -261,7 +297,7 @@ void outsb(unsigned int port, const void *from, int len) BUG(); } - __raw_writesb(ISAIO_BASE + off, from, len); + __raw_writesb((void __iomem *)ISAIO_BASE + off, from, len); } void insb(unsigned int port, void *from, int len) @@ -276,7 +312,7 @@ void insb(unsigned int port, void *from, int len) BUG(); } - __raw_readsb(ISAIO_BASE + off, from, len); + __raw_readsb((void __iomem *)ISAIO_BASE + off, from, len); } EXPORT_SYMBOL(outsb); @@ -294,7 +330,7 @@ void outsw(unsigned int port, const void *from, int len) BUG(); } - __raw_writesw(ISAIO_BASE + off, from, len); + __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len); } void insw(unsigned int port, void *from, int len) @@ -309,18 +345,35 @@ void insw(unsigned int port, void *from, int len) BUG(); } - __raw_readsw(ISAIO_BASE + off, from, len); + __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len); } EXPORT_SYMBOL(outsw); EXPORT_SYMBOL(insw); +/* + * We implement these as 16-bit insw/outsw, mainly for + * 3c589 cards. + */ void outsl(unsigned int port, const void *from, int len) { - panic("outsl not supported on this architecture"); + u32 off = port << 1; + + if (SUPERIO_PORT(port) || port & 3) + BUG(); + + __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len << 1); } void insl(unsigned int port, void *from, int len) { - panic("insl not supported on this architecture"); + u32 off = port << 1; + + if (SUPERIO_PORT(port) || port & 3) + BUG(); + + __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len << 1); } + +EXPORT_SYMBOL(outsl); +EXPORT_SYMBOL(insl);