X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmach-ixp4xx%2FKconfig;fp=arch%2Farm%2Fmach-ixp4xx%2FKconfig;h=5bf50a2a737ddcff4ee342560828519f6f876b9a;hb=64ba3f394c830ec48a1c31b53dcae312c56f1604;hp=57f23b4653927a5fcb83c9eaed9cce6cd17ca583;hpb=be1e6109ac94a859551f8e1774eb9a8469fe055c;p=linux-2.6.git diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 57f23b465..5bf50a2a7 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -11,7 +11,6 @@ comment "IXP4xx Platforms" config MACH_NSLU2 bool prompt "Linksys NSLU2" - select PCI help Say 'Y' here if you want your kernel to support Linksys's NSLU2 NAS device. For more information on this platform, @@ -19,7 +18,6 @@ config MACH_NSLU2 config ARCH_AVILA bool "Avila" - select PCI help Say 'Y' here if you want your kernel to support the Gateworks Avila Network Platform. For more information on this platform, @@ -27,7 +25,6 @@ config ARCH_AVILA config ARCH_ADI_COYOTE bool "Coyote" - select PCI help Say 'Y' here if you want your kernel to support the ADI Engineering Coyote Gateway Reference Platform. For more @@ -75,7 +72,6 @@ config ARCH_PRPMC1100 config MACH_NAS100D bool prompt "NAS100D" - select PCI help Say 'Y' here if you want your kernel to support Iomega's NAS 100d device. For more information on this platform, @@ -100,7 +96,6 @@ config CPU_IXP46X config MACH_GTWX5715 bool "Gemtek WX5715 (Linksys WRV54G)" depends on ARCH_IXP4XX - select PCI help This board is currently inside the Linksys WRV54G Gateways. @@ -115,16 +110,11 @@ config MACH_GTWX5715 "High Speed" UART is n/c (as far as I can tell) 20 Pin ARM/Xscale JTAG interface on J2 -comment "IXP4xx Options" -config DMABOUNCE - bool - default y - depends on PCI +comment "IXP4xx Options" config IXP4XX_INDIRECT_PCI bool "Use indirect PCI memory access" - depends on PCI help IXP4xx provides two methods of accessing PCI memory space: @@ -138,7 +128,7 @@ config IXP4XX_INDIRECT_PCI 2) If > 64MB of memory space is required, the IXP4xx can be configured to use indirect registers to access PCI This allows for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. - The disadvantage of this is that every PCI access requires + The disadvantadge of this is that every PCI access requires three local register accesses plus a spinlock, but in some cases the performance hit is acceptable. In addition, you cannot mmap() PCI devices in this case due to the indirect nature