X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmach-ixp4xx%2Fcommon.c;h=00b761ff0f9ce75b76fcf60217919eb1acbf308b;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=a4edbe0eb909674efd824b1392d3f9e407395a82;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index a4edbe0eb..00b761ff0 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -38,93 +39,34 @@ #include #include - -/************************************************************************* - * GPIO acces functions - *************************************************************************/ - -/* - * Configure GPIO line for input, interrupt, or output operation - * - * TODO: Enable/disable the irq_desc based on interrupt or output mode. - * TODO: Should these be named ixp4xx_gpio_? - */ -void gpio_line_config(u8 line, u32 style) -{ - u32 enable; - volatile u32 *int_reg; - u32 int_style; - - enable = *IXP4XX_GPIO_GPOER; - - if (style & IXP4XX_GPIO_OUT) { - enable &= ~((1) << line); - } else if (style & IXP4XX_GPIO_IN) { - enable |= ((1) << line); - - switch (style & IXP4XX_GPIO_INTSTYLE_MASK) - { - case (IXP4XX_GPIO_ACTIVE_HIGH): - int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; - break; - case (IXP4XX_GPIO_ACTIVE_LOW): - int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; - break; - case (IXP4XX_GPIO_RISING_EDGE): - int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; - break; - case (IXP4XX_GPIO_FALLING_EDGE): - int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; - break; - case (IXP4XX_GPIO_TRANSITIONAL): - int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; - break; - default: - int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; - break; - } - - if (line >= 8) { /* pins 8-15 */ - line -= 8; - int_reg = IXP4XX_GPIO_GPIT2R; - } - else { /* pins 0-7 */ - int_reg = IXP4XX_GPIO_GPIT1R; - } - - /* Clear the style for the appropriate pin */ - *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << - (line * IXP4XX_GPIO_STYLE_SIZE)); - - /* Set the new style */ - *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); - } - - *IXP4XX_GPIO_GPOER = enable; -} - -EXPORT_SYMBOL(gpio_line_config); - /************************************************************************* * IXP4xx chipset I/O mapping *************************************************************************/ static struct map_desc ixp4xx_io_desc[] __initdata = { { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, - .physical = IXP4XX_PERIPHERAL_BASE_PHYS, + .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), .length = IXP4XX_PERIPHERAL_REGION_SIZE, .type = MT_DEVICE }, { /* Expansion Bus Config Registers */ .virtual = IXP4XX_EXP_CFG_BASE_VIRT, - .physical = IXP4XX_EXP_CFG_BASE_PHYS, + .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), .length = IXP4XX_EXP_CFG_REGION_SIZE, .type = MT_DEVICE }, { /* PCI Registers */ .virtual = IXP4XX_PCI_CFG_BASE_VIRT, - .physical = IXP4XX_PCI_CFG_BASE_PHYS, + .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), .length = IXP4XX_PCI_CFG_REGION_SIZE, .type = MT_DEVICE + }, +#ifdef CONFIG_DEBUG_LL + { /* Debug UART mapping */ + .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, + .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), + .length = IXP4XX_DEBUG_UART_REGION_SIZE, + .type = MT_DEVICE } +#endif }; void __init ixp4xx_map_io(void) @@ -138,48 +80,148 @@ void __init ixp4xx_map_io(void) * * TODO: GPIO IRQs should be marked invalid until the user of the IRQ * (be it PCI or something else) configures that GPIO line - * as an IRQ. Also, we should use a different chip structure for - * level-based GPIO vs edge-based GPIO. Currently nobody needs this as - * all HW that's publically available uses level IRQs, so we'll - * worry about it if/when we have HW to test. + * as an IRQ. **************************************************************************/ -static void ixp4xx_irq_mask(unsigned int irq) +enum ixp4xx_irq_type { + IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE +}; + +static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); + +/* + * IRQ -> GPIO mapping table + */ +static signed char irq2gpio[32] = { + -1, -1, -1, -1, -1, -1, 0, 1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, -1, -1, +}; + +static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) { - *IXP4XX_ICMR &= ~(1 << irq); + int line = irq2gpio[irq]; + u32 int_style; + enum ixp4xx_irq_type irq_type; + volatile u32 *int_reg; + + /* + * Only for GPIO IRQs + */ + if (line < 0) + return -EINVAL; + + switch (type){ + case IRQT_BOTHEDGE: + int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; + irq_type = IXP4XX_IRQ_EDGE; + break; + case IRQT_RISING: + int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; + irq_type = IXP4XX_IRQ_EDGE; + break; + case IRQT_FALLING: + int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; + irq_type = IXP4XX_IRQ_EDGE; + break; + case IRQT_HIGH: + int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; + irq_type = IXP4XX_IRQ_LEVEL; + break; + case IRQT_LOW: + int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; + irq_type = IXP4XX_IRQ_LEVEL; + break; + default: + return -EINVAL; + } + ixp4xx_config_irq(irq, irq_type); + + if (line >= 8) { /* pins 8-15 */ + line -= 8; + int_reg = IXP4XX_GPIO_GPIT2R; + } else { /* pins 0-7 */ + int_reg = IXP4XX_GPIO_GPIT1R; + } + + /* Clear the style for the appropriate pin */ + *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << + (line * IXP4XX_GPIO_STYLE_SIZE)); + + *IXP4XX_GPIO_GPISR = (1 << line); + + /* Set the new style */ + *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); + + /* Configure the line as an input */ + gpio_line_config(line, IXP4XX_GPIO_IN); + + return 0; } -static void ixp4xx_irq_mask_ack(unsigned int irq) +static void ixp4xx_irq_mask(unsigned int irq) { - ixp4xx_irq_mask(irq); + if (cpu_is_ixp46x() && irq >= 32) + *IXP4XX_ICMR2 &= ~(1 << (irq - 32)); + else + *IXP4XX_ICMR &= ~(1 << irq); } static void ixp4xx_irq_unmask(unsigned int irq) { - static int irq2gpio[NR_IRQS] = { - -1, -1, -1, -1, -1, -1, 0, 1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 2, 3, 4, 5, 6, - 7, 8, 9, 10, 11, 12, -1, -1, - }; - int line = irq2gpio[irq]; + if (cpu_is_ixp46x() && irq >= 32) + *IXP4XX_ICMR2 |= (1 << (irq - 32)); + else + *IXP4XX_ICMR |= (1 << irq); +} + +static void ixp4xx_irq_ack(unsigned int irq) +{ + int line = (irq < 32) ? irq2gpio[irq] : -1; - /* - * This only works for LEVEL gpio IRQs as per the IXP4xx developer's - * manual. If edge-triggered, need to move it to the mask_ack. - * Nobody seems to be using the edge-triggered mode on the GPIOs. - */ if (line >= 0) - gpio_line_isr_clear(line); + *IXP4XX_GPIO_GPISR = (1 << line); +} - *IXP4XX_ICMR |= (1 << irq); +/* + * Level triggered interrupts on GPIO lines can only be cleared when the + * interrupt condition disappears. + */ +static void ixp4xx_irq_level_unmask(unsigned int irq) +{ + ixp4xx_irq_ack(irq); + ixp4xx_irq_unmask(irq); } -static struct irqchip ixp4xx_irq_chip = { - .ack = ixp4xx_irq_mask_ack, - .mask = ixp4xx_irq_mask, - .unmask = ixp4xx_irq_unmask, +static struct irqchip ixp4xx_irq_level_chip = { + .ack = ixp4xx_irq_mask, + .mask = ixp4xx_irq_mask, + .unmask = ixp4xx_irq_level_unmask, + .set_type = ixp4xx_set_irq_type, }; +static struct irqchip ixp4xx_irq_edge_chip = { + .ack = ixp4xx_irq_ack, + .mask = ixp4xx_irq_mask, + .unmask = ixp4xx_irq_unmask, + .set_type = ixp4xx_set_irq_type, +}; + +static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type) +{ + switch (type) { + case IXP4XX_IRQ_LEVEL: + set_irq_chip(irq, &ixp4xx_irq_level_chip); + set_irq_handler(irq, do_level_IRQ); + break; + case IXP4XX_IRQ_EDGE: + set_irq_chip(irq, &ixp4xx_irq_edge_chip); + set_irq_handler(irq, do_edge_IRQ); + break; + } + set_irq_flags(irq, IRQF_VALID); +} + void __init ixp4xx_init_irq(void) { int i = 0; @@ -190,12 +232,17 @@ void __init ixp4xx_init_irq(void) /* Disable all interrupt */ *IXP4XX_ICMR = 0x0; - for(i = 0; i < NR_IRQS; i++) - { - set_irq_chip(i, &ixp4xx_irq_chip); - set_irq_handler(i, do_level_IRQ); - set_irq_flags(i, IRQF_VALID); + if (cpu_is_ixp46x()) { + /* Route upper 32 sources to IRQ instead of FIQ */ + *IXP4XX_ICLR2 = 0x00; + + /* Disable upper 32 interrupts */ + *IXP4XX_ICMR2 = 0x00; } + + /* Default to all level triggered */ + for(i = 0; i < NR_IRQS; i++) + ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL); } @@ -207,7 +254,7 @@ void __init ixp4xx_init_irq(void) static unsigned volatile last_jiffy_time; -#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC) +#define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC) /* IRQs are disabled before entering here from do_gettimeofday() */ static unsigned long ixp4xx_gettimeoffset(void) @@ -221,30 +268,32 @@ static unsigned long ixp4xx_gettimeoffset(void) static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { + write_seqlock(&xtime_lock); + /* Clear Pending Interrupt by writing '1' to it */ *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; /* * Catch up with the real idea of time */ - do { + while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) { timer_tick(regs); last_jiffy_time += LATCH; - } while((*IXP4XX_OSTS - last_jiffy_time) > LATCH); + } + + write_sequnlock(&xtime_lock); return IRQ_HANDLED; } static struct irqaction ixp4xx_timer_irq = { .name = "IXP4xx Timer Tick", - .flags = SA_INTERRUPT, - .handler = ixp4xx_timer_interrupt + .flags = SA_INTERRUPT | SA_TIMER, + .handler = ixp4xx_timer_interrupt, }; -void __init ixp4xx_init_time(void) +static void __init ixp4xx_timer_init(void) { - gettimeoffset = ixp4xx_gettimeoffset; - /* Clear Pending Interrupt by writing '1' to it */ *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; @@ -259,4 +308,61 @@ void __init ixp4xx_init_time(void) setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq); } +struct sys_timer ixp4xx_timer = { + .init = ixp4xx_timer_init, + .offset = ixp4xx_gettimeoffset, +}; + +static struct resource ixp46x_i2c_resources[] = { + [0] = { + .start = 0xc8011000, + .end = 0xc801101c, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IXP4XX_I2C, + .end = IRQ_IXP4XX_I2C, + .flags = IORESOURCE_IRQ + } +}; + +/* + * I2C controller. The IXP46x uses the same block as the IOP3xx, so + * we just use the same device name. + */ +static struct platform_device ixp46x_i2c_controller = { + .name = "IOP3xx-I2C", + .id = 0, + .num_resources = 2, + .resource = ixp46x_i2c_resources +}; + +static struct platform_device *ixp46x_devices[] __initdata = { + &ixp46x_i2c_controller +}; + +unsigned long ixp4xx_exp_bus_size; +EXPORT_SYMBOL(ixp4xx_exp_bus_size); + +void __init ixp4xx_sys_init(void) +{ + ixp4xx_exp_bus_size = SZ_16M; + + if (cpu_is_ixp46x()) { + int region; + + platform_add_devices(ixp46x_devices, + ARRAY_SIZE(ixp46x_devices)); + + for (region = 0; region < 7; region++) { + if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) { + ixp4xx_exp_bus_size = SZ_32M; + break; + } + } + } + + printk("IXP4xx: Using %luMiB expansion bus window size\n", + ixp4xx_exp_bus_size >> 20); +}