X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmach-s3c2410%2Firq.c;h=66d8c068e940b9436693361f7bdd5dc5f941bc6e;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=1951a0323f178b6a66effef6fedb80f93177588f;hpb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;p=linux-2.6.git diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 1951a0323..66d8c068e 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c @@ -33,9 +33,23 @@ * * 05-Oct-2004 Ben Dooks * Tidy up KF's patch and sort out new release + * + * 05-Oct-2004 Ben Dooks + * Add support for power management controls + * + * 04-Nov-2004 Ben Dooks + * Fix standard IRQ wake for EINT0..4 and RTC + * + * 22-Feb-2005 Ben Dooks + * Fixed edge-triggering on ADC IRQ + * + * 28-Jun-2005 Ben Dooks + * Mark IRQ_LCD valid + * + * 25-Jul-2005 Ben Dooks + * Split the S3C2440 IRQ code to seperate file */ - #include #include #include @@ -52,9 +66,69 @@ #include #include +#include "cpu.h" +#include "pm.h" +#include "irq.h" + +/* wakeup irq control */ + +#ifdef CONFIG_PM + +/* state for IRQs over sleep */ + +/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources + * + * set bit to 1 in allow bitfield to enable the wakeup settings on it +*/ + +unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; +unsigned long s3c_irqwake_intmask = 0xffffffffL; +unsigned long s3c_irqwake_eintallow = 0x0000fff0L; +unsigned long s3c_irqwake_eintmask = 0xffffffffL; + +static int +s3c_irq_wake(unsigned int irqno, unsigned int state) +{ + unsigned long irqbit = 1 << (irqno - IRQ_EINT0); + + if (!(s3c_irqwake_intallow & irqbit)) + return -ENOENT; + + printk(KERN_INFO "wake %s for irq %d\n", + state ? "enabled" : "disabled", irqno); + + if (!state) + s3c_irqwake_intmask |= irqbit; + else + s3c_irqwake_intmask &= ~irqbit; + + return 0; +} + +static int +s3c_irqext_wake(unsigned int irqno, unsigned int state) +{ + unsigned long bit = 1L << (irqno - EXTINT_OFF); + + if (!(s3c_irqwake_eintallow & bit)) + return -ENOENT; + + printk(KERN_INFO "wake %s for irq %d\n", + state ? "enabled" : "disabled", irqno); + + if (!state) + s3c_irqwake_eintmask |= bit; + else + s3c_irqwake_eintmask &= ~bit; + + return 0; +} + +#else +#define s3c_irqext_wake NULL +#define s3c_irq_wake NULL +#endif -#define irqdbf(x...) -#define irqdbf2(x...) static void s3c_irq_mask(unsigned int irqno) @@ -106,24 +180,24 @@ s3c_irq_unmask(unsigned int irqno) __raw_writel(mask, S3C2410_INTMSK); } -static struct irqchip s3c_irq_level_chip = { +struct irqchip s3c_irq_level_chip = { .ack = s3c_irq_maskack, .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask + .unmask = s3c_irq_unmask, + .set_wake = s3c_irq_wake }; static struct irqchip s3c_irq_chip = { .ack = s3c_irq_ack, .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask + .unmask = s3c_irq_unmask, + .set_wake = s3c_irq_wake }; /* S3C2410_EINTMASK * S3C2410_EINTPEND */ -#define EXTINT_OFF (IRQ_EINT4 - 4) - static void s3c_irqext_mask(unsigned int irqno) { @@ -193,8 +267,8 @@ s3c_irqext_unmask(unsigned int irqno) static int s3c_irqext_type(unsigned int irq, unsigned int type) { - unsigned long extint_reg; - unsigned long gpcon_reg; + void __iomem *extint_reg; + void __iomem *gpcon_reg; unsigned long gpcon_offset, extint_offset; unsigned long newvalue = 0, value; @@ -276,14 +350,16 @@ static struct irqchip s3c_irqext_chip = { .mask = s3c_irqext_mask, .unmask = s3c_irqext_unmask, .ack = s3c_irqext_ack, - .type = s3c_irqext_type + .set_type = s3c_irqext_type, + .set_wake = s3c_irqext_wake }; static struct irqchip s3c_irq_eint0t4 = { .ack = s3c_irq_ack, .mask = s3c_irq_mask, .unmask = s3c_irq_unmask, - .type = s3c_irqext_type + .set_wake = s3c_irq_wake, + .set_type = s3c_irqext_type, }; /* mask values for the parent registers for each of the interrupt types */ @@ -292,68 +368,6 @@ static struct irqchip s3c_irq_eint0t4 = { #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0)) #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) -#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) - -static inline void -s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, - int subcheck) -{ - unsigned long mask; - unsigned long submask; - - submask = __raw_readl(S3C2410_INTSUBMSK); - mask = __raw_readl(S3C2410_INTMSK); - - submask |= (1UL << (irqno - IRQ_S3CUART_RX0)); - - /* check to see if we need to mask the parent IRQ */ - - if ((submask & subcheck) == subcheck) { - __raw_writel(mask | parentbit, S3C2410_INTMSK); - } - - /* write back masks */ - __raw_writel(submask, S3C2410_INTSUBMSK); - -} - -static inline void -s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) -{ - unsigned long mask; - unsigned long submask; - - submask = __raw_readl(S3C2410_INTSUBMSK); - mask = __raw_readl(S3C2410_INTMSK); - - submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0)); - mask &= ~parentbit; - - /* write back masks */ - __raw_writel(submask, S3C2410_INTSUBMSK); - __raw_writel(mask, S3C2410_INTMSK); -} - - -static inline void -s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group) -{ - unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); - - s3c_irqsub_mask(irqno, parentmask, group); - - __raw_writel(bit, S3C2410_SUBSRCPND); - - /* only ack parent if we've got all the irqs (seems we must - * ack, all and hope that the irq system retriggers ok when - * the interrupt goes off again) - */ - - if (1) { - __raw_writel(parentmask, S3C2410_SRCPND); - __raw_writel(parentmask, S3C2410_INTPND); - } -} /* UART0 */ @@ -451,7 +465,7 @@ s3c_irq_adc_unmask(unsigned int irqno) static void s3c_irq_adc_ack(unsigned int irqno) { - s3c_irqsub_maskack(irqno, INTMSK_ADCPARENT, 3 << 9); + s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); } static struct irqchip s3c_irq_adc = { @@ -482,11 +496,11 @@ static void s3c_irq_demux_adc(unsigned int irq, if (subsrc != 0) { if (subsrc & 1) { mydesc = irq_desc + IRQ_TC; - mydesc->handle( IRQ_TC, mydesc, regs); + desc_handle_irq(IRQ_TC, mydesc, regs); } if (subsrc & 2) { mydesc = irq_desc + IRQ_ADC; - mydesc->handle(IRQ_ADC, mydesc, regs); + desc_handle_irq(IRQ_ADC, mydesc, regs); } } } @@ -515,17 +529,17 @@ static void s3c_irq_demux_uart(unsigned int start, desc = irq_desc + start; if (subsrc & 1) - desc->handle(start, desc, regs); + desc_handle_irq(start, desc, regs); desc++; if (subsrc & 2) - desc->handle(start+1, desc, regs); + desc_handle_irq(start+1, desc, regs); desc++; if (subsrc & 4) - desc->handle(start+2, desc, regs); + desc_handle_irq(start+2, desc, regs); } } @@ -558,12 +572,13 @@ s3c_irq_demux_uart2(unsigned int irq, s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs); } -/* s3c2410_init_irq + +/* s3c24xx_init_irq * * Initialise S3C2410 IRQ system */ -void __init s3c2410_init_irq(void) +void __init s3c24xx_init_irq(void) { unsigned long pend; unsigned long last; @@ -624,7 +639,6 @@ void __init s3c2410_init_irq(void) case IRQ_UART0: case IRQ_UART1: case IRQ_UART2: - case IRQ_LCD: case IRQ_ADCPARENT: set_irq_chip(irqno, &s3c_irq_level_chip); set_irq_handler(irqno, do_level_IRQ);