X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmach-s3c2410%2Fmach-bast.c;h=b8b76757ec54a70272a9107b06f5b554a50d299f;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=f7526690751e01a0443c60b90a69abc2bea0bd15;hpb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;p=linux-2.6.git diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index f75266907..b8b76757e 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s3c2410/mach-bast.c * - * Copyright (c) 2003,2004 Simtec Electronics + * Copyright (c) 2003-2005 Simtec Electronics * Ben Dooks * * http://www.simtec.co.uk/products/EB2410ITX/ @@ -8,16 +8,6 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * Modifications: - * 14-Sep-2004 BJD USB power control - * 20-Aug-2004 BJD Added s3c2410_board struct - * 18-Aug-2004 BJD Added platform devices from default set - * 16-May-2003 BJD Created initial version - * 16-Aug-2003 BJD Fixed header files and copyright, added URL - * 05-Sep-2003 BJD Moved to v2.6 kernel - * 06-Jan-2003 BJD Updates for - * 18-Jan-2003 BJD Added serial port configuration */ #include @@ -26,13 +16,17 @@ #include #include #include -#include +#include +#include +#include #include #include #include #include +#include +#include #include #include @@ -41,57 +35,93 @@ //#include #include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include -#include "s3c2410.h" +#include "clock.h" #include "devs.h" #include "cpu.h" #include "usb-simtec.h" +#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" + /* macros for virtual address mods for the io space entries */ -#define VA_C5(item) ((item) + BAST_VAM_CS5) -#define VA_C4(item) ((item) + BAST_VAM_CS4) -#define VA_C3(item) ((item) + BAST_VAM_CS3) -#define VA_C2(item) ((item) + BAST_VAM_CS2) +#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) +#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) +#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) +#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) /* macros to modify the physical addresses for io space */ -#define PA_CS2(item) ((item) + S3C2410_CS2) -#define PA_CS3(item) ((item) + S3C2410_CS3) -#define PA_CS4(item) ((item) + S3C2410_CS4) -#define PA_CS5(item) ((item) + S3C2410_CS5) +#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2)) +#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3)) +#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4)) +#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5)) static struct map_desc bast_iodesc[] __initdata = { /* ISA IO areas */ - - { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - - /* we could possibly compress the next set down into a set of smaller tables - * pagetables, but that would mean using an L2 section, and it still means - * we cannot actually feed the same register to an LDR due to 16K spacing - */ - + { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = PA_CS2(BAST_PA_ISAIO), + .length = SZ_16M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = PA_CS3(BAST_PA_ISAIO), + .length = SZ_16M, + .type = MT_DEVICE, + }, /* bast CPLD control registers, and external interrupt controls */ - { BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE }, - { BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE }, - { BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE }, - { BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE }, - + { + .virtual = (u32)BAST_VA_CTRL1, + .pfn = __phys_to_pfn(BAST_PA_CTRL1), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (u32)BAST_VA_CTRL2, + .pfn = __phys_to_pfn(BAST_PA_CTRL2), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (u32)BAST_VA_CTRL3, + .pfn = __phys_to_pfn(BAST_PA_CTRL3), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (u32)BAST_VA_CTRL4, + .pfn = __phys_to_pfn(BAST_PA_CTRL4), + .length = SZ_1M, + .type = MT_DEVICE, + }, /* PC104 IRQ mux */ - { BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE }, - { BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE }, - { BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE }, - - /* onboard 8bit lcd port */ - - { BAST_VA_LCD_RCMD1, BAST_PA_LCD_RCMD1, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_WCMD1, BAST_PA_LCD_WCMD1, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_RDATA1, BAST_PA_LCD_RDATA1, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_WDATA1, BAST_PA_LCD_WDATA1, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_RCMD2, BAST_PA_LCD_RCMD2, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_WCMD2, BAST_PA_LCD_WCMD2, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_RDATA2, BAST_PA_LCD_RDATA2, SZ_1M, MT_DEVICE }, - { BAST_VA_LCD_WDATA2, BAST_PA_LCD_WDATA2, SZ_1M, MT_DEVICE }, + { + .virtual = (u32)BAST_VA_PC104_IRQREQ, + .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (u32)BAST_VA_PC104_IRQRAW, + .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (u32)BAST_VA_PC104_IRQMASK, + .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK), + .length = SZ_1M, + .type = MT_DEVICE, + }, /* peripheral space... one for each of fast/slow/byte/16bit */ /* note, ide is only decoded in word space, even though some registers @@ -100,9 +130,7 @@ static struct map_desc bast_iodesc[] __initdata = { /* slow, byte */ { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C2(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE }, { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - { VA_C2(BAST_VA_DM9000), PA_CS2(BAST_PA_DM9000), SZ_1M, MT_DEVICE }, { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, @@ -111,9 +139,7 @@ static struct map_desc bast_iodesc[] __initdata = { /* slow, word */ { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C3(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE }, { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - { VA_C3(BAST_VA_DM9000), PA_CS3(BAST_PA_DM9000), SZ_1M, MT_DEVICE }, { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, @@ -122,9 +148,7 @@ static struct map_desc bast_iodesc[] __initdata = { /* fast, byte */ { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C4(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE }, { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - { VA_C4(BAST_VA_DM9000), PA_CS4(BAST_PA_DM9000), SZ_1M, MT_DEVICE }, { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, @@ -133,9 +157,7 @@ static struct map_desc bast_iodesc[] __initdata = { /* fast, word */ { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C5(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE }, { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - { VA_C5(BAST_VA_DM9000), PA_CS5(BAST_PA_DM9000), SZ_1M, MT_DEVICE }, { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, @@ -146,35 +168,50 @@ static struct map_desc bast_iodesc[] __initdata = { #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -/* base baud rate for all our UARTs */ -static unsigned long bast_serial_clock = 24*1000*1000; +static struct s3c24xx_uart_clksrc bast_serial_clocks[] = { + [0] = { + .name = "uclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + } +}; -static struct s3c2410_uartcfg bast_uartcfgs[] = { + +static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .clock = &bast_serial_clock, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, + .clocks = bast_serial_clocks, + .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, [1] = { .hwport = 1, .flags = 0, - - .clock = &bast_serial_clock, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, + .clocks = bast_serial_clocks, + .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, /* port 2 is not actually used */ [2] = { .hwport = 2, .flags = 0, - .clock = &bast_serial_clock, .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, + .clocks = bast_serial_clocks, + .clocks_size = ARRAY_SIZE(bast_serial_clocks), } }; @@ -195,6 +232,215 @@ static struct platform_device bast_device_nor = { .resource = bast_nor_resource, }; +/* NAND Flash on BAST board */ + + +static int smartmedia_map[] = { 0 }; +static int chip0_map[] = { 1 }; +static int chip1_map[] = { 2 }; +static int chip2_map[] = { 3 }; + +static struct mtd_partition bast_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0, + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_16K, + .offset = SZ_16K, + }, + [2] = { + .name = "user", + .offset = SZ_4M, + .size = MTDPART_SIZ_FULL, + } +}; + +/* the bast has 4 selectable slots for nand-flash, the three + * on-board chip areas, as well as the external SmartMedia + * slot. + * + * Note, there is no current hot-plug support for the SmartMedia + * socket. +*/ + +static struct s3c2410_nand_set bast_nand_sets[] = { + [0] = { + .name = "SmartMedia", + .nr_chips = 1, + .nr_map = smartmedia_map, + .nr_partitions = ARRAY_SIZE(bast_default_nand_part), + .partitions = bast_default_nand_part, + }, + [1] = { + .name = "chip0", + .nr_chips = 1, + .nr_map = chip0_map, + .nr_partitions = ARRAY_SIZE(bast_default_nand_part), + .partitions = bast_default_nand_part, + }, + [2] = { + .name = "chip1", + .nr_chips = 1, + .nr_map = chip1_map, + .nr_partitions = ARRAY_SIZE(bast_default_nand_part), + .partitions = bast_default_nand_part, + }, + [3] = { + .name = "chip2", + .nr_chips = 1, + .nr_map = chip2_map, + .nr_partitions = ARRAY_SIZE(bast_default_nand_part), + .partitions = bast_default_nand_part, + } +}; + +static void bast_nand_select(struct s3c2410_nand_set *set, int slot) +{ + unsigned int tmp; + + slot = set->nr_map[slot] & 3; + + pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", + slot, set, set->nr_map); + + tmp = __raw_readb(BAST_VA_CTRL2); + tmp &= BAST_CPLD_CTLR2_IDERST; + tmp |= slot; + tmp |= BAST_CPLD_CTRL2_WNAND; + + pr_debug("bast_nand: ctrl2 now %02x\n", tmp); + + __raw_writeb(tmp, BAST_VA_CTRL2); +} + +static struct s3c2410_platform_nand bast_nand_info = { + .tacls = 30, + .twrph0 = 60, + .twrph1 = 60, + .nr_sets = ARRAY_SIZE(bast_nand_sets), + .sets = bast_nand_sets, + .select_chip = bast_nand_select, +}; + +/* DM9000 */ + +static struct resource bast_dm9k_resource[] = { + [0] = { + .start = S3C2410_CS5 + BAST_PA_DM9000, + .end = S3C2410_CS5 + BAST_PA_DM9000 + 3, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40, + .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_DM9000, + .end = IRQ_DM9000, + .flags = IORESOURCE_IRQ, + } + +}; + +/* for the moment we limit ourselves to 16bit IO until some + * better IO routines can be written and tested +*/ + +static struct dm9000_plat_data bast_dm9k_platdata = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device bast_device_dm9k = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(bast_dm9k_resource), + .resource = bast_dm9k_resource, + .dev = { + .platform_data = &bast_dm9k_platdata, + } +}; + +/* serial devices */ + +#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO) +#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ) +#define SERIAL_CLK (1843200) + +static struct plat_serial8250_port bast_sio_data[] = { + [0] = { + .mapbase = SERIAL_BASE + 0x2f8, + .irq = IRQ_PCSERIAL1, + .flags = SERIAL_FLAGS, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = SERIAL_CLK, + }, + [1] = { + .mapbase = SERIAL_BASE + 0x3f8, + .irq = IRQ_PCSERIAL2, + .flags = SERIAL_FLAGS, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = SERIAL_CLK, + }, + { } +}; + +static struct platform_device bast_sio = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = &bast_sio_data, + }, +}; + +/* we have devices on the bus which cannot work much over the + * standard 100KHz i2c bus frequency +*/ + +static struct s3c2410_platform_i2c bast_i2c_info = { + .flags = 0, + .slave_addr = 0x10, + .bus_freq = 100*1000, + .max_freq = 130*1000, +}; + + +static struct s3c2410fb_mach_info __initdata bast_lcd_info = { + .width = 640, + .height = 480, + + .xres = { + .min = 320, + .max = 1024, + .defval = 640, + }, + + .yres = { + .min = 240, + .max = 600, + .defval = 480, + }, + + .bpp = { + .min = 4, + .max = 16, + .defval = 8, + }, + + .regs = { + .lcdcon1 = 0x00000176, + .lcdcon2 = 0x1d77c7c2, + .lcdcon3 = 0x013a7f13, + .lcdcon4 = 0x00000057, + .lcdcon5 = 0x00014b02, + } +}; + /* Standard BAST devices */ static struct platform_device *bast_devices[] __initdata = { @@ -204,37 +450,64 @@ static struct platform_device *bast_devices[] __initdata = { &s3c_device_i2c, &s3c_device_iis, &s3c_device_rtc, - &bast_device_nor + &s3c_device_nand, + &bast_device_nor, + &bast_device_dm9k, + &bast_sio, +}; + +static struct clk *bast_clocks[] = { + &s3c24xx_dclk0, + &s3c24xx_dclk1, + &s3c24xx_clkout0, + &s3c24xx_clkout1, + &s3c24xx_uclk, }; -static struct s3c2410_board bast_board __initdata = { +static struct s3c24xx_board bast_board __initdata = { .devices = bast_devices, - .devices_count = ARRAY_SIZE(bast_devices) + .devices_count = ARRAY_SIZE(bast_devices), + .clocks = bast_clocks, + .clocks_count = ARRAY_SIZE(bast_clocks), }; -void __init bast_map_io(void) +static void __init bast_map_io(void) { + /* initialise the clocks */ + + s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.rate = 12*1000*1000; + + s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.rate = 24*1000*1000; + + s3c24xx_clkout0.parent = &s3c24xx_dclk0; + s3c24xx_clkout1.parent = &s3c24xx_dclk1; + + s3c24xx_uclk.parent = &s3c24xx_clkout1; + + s3c_device_nand.dev.platform_data = &bast_nand_info; + s3c_device_i2c.dev.platform_data = &bast_i2c_info; + s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); - s3c2410_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); - s3c2410_set_board(&bast_board); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); + s3c24xx_set_board(&bast_board); usb_simtec_init(); } -void __init bast_init_irq(void) -{ - s3c2410_init_irq(); -} - -void __init bast_init_time(void) +static void __init bast_init(void) { - s3c2410_init_time(); + s3c24xx_fb_set_platdata(&bast_lcd_info); } MACHINE_START(BAST, "Simtec-BAST") - MAINTAINER("Ben Dooks ") - BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART) - BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100) - MAPIO(bast_map_io) - INITIRQ(bast_init_irq) - INITTIME(bast_init_time) + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = bast_map_io, + .init_irq = s3c24xx_init_irq, + .init_machine = bast_init, + .timer = &s3c24xx_timer, MACHINE_END