X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmm%2Fproc-arm1020e.S;fp=arch%2Farm%2Fmm%2Fproc-arm1020e.S;h=7375fe930f7273520fe69c47f5141e6339e57f7d;hb=64ba3f394c830ec48a1c31b53dcae312c56f1604;hp=89b1d6d3d7c0fc572be129aa38361da0b2736669;hpb=be1e6109ac94a859551f8e1774eb9a8469fe055c;p=linux-2.6.git diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 89b1d6d3d..7375fe930 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -3,7 +3,6 @@ * * Copyright (C) 2000 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd. - * hacked for non-paged-MM by Hyok S. Choi, 2003. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,15 +25,14 @@ * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt */ #include +#include #include #include #include -#include #include #include #include - -#include "proc-macros.S" +#include /* * This is the maximum size of an area which will be invalidated @@ -103,9 +101,7 @@ ENTRY(cpu_arm1020e_reset) mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches mcr p15, 0, ip, c7, c10, 4 @ drain WB -#ifdef CONFIG_MMU mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs -#endif mrc p15, 0, ip, c1, c0, 0 @ ctrl register bic ip, ip, #0x000f @ ............wcam bic ip, ip, #0x1100 @ ...i...s........ @@ -348,7 +344,6 @@ ENTRY(cpu_arm1020e_dcache_clean_area) */ .align 5 ENTRY(cpu_arm1020e_switch_mm) -#ifdef CONFIG_MMU #ifndef CONFIG_CPU_DCACHE_DISABLE mcr p15, 0, r3, c7, c10, 4 mov r1, #0xF @ 16 segments @@ -372,7 +367,6 @@ ENTRY(cpu_arm1020e_switch_mm) mcr p15, 0, r1, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs -#endif mov pc, lr /* @@ -382,7 +376,6 @@ ENTRY(cpu_arm1020e_switch_mm) */ .align 5 ENTRY(cpu_arm1020e_set_pte) -#ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY @@ -410,7 +403,6 @@ ENTRY(cpu_arm1020e_set_pte) #ifndef CONFIG_CPU_DCACHE_DISABLE mcr p15, 0, r0, c7, c10, 1 @ clean D entry #endif -#endif /* CONFIG_MMU */ mov pc, lr __INIT @@ -420,14 +412,12 @@ __arm1020e_setup: mov r0, #0 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 -#ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 -#endif - adr r5, arm1020e_crval - ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0 @ get control register v4 + ldr r5, arm1020e_cr1_clear bic r0, r0, r5 - orr r0, r0, r6 + ldr r5, arm1020e_cr1_set + orr r0, r0, r5 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .R.. .... .... .... #endif @@ -439,9 +429,12 @@ __arm1020e_setup: * .RVI ZFRS BLDP WCAM * .011 1001 ..11 0101 */ - .type arm1020e_crval, #object -arm1020e_crval: - crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930 + .type arm1020e_cr1_clear, #object + .type arm1020e_cr1_set, #object +arm1020e_cr1_clear: + .word 0x5f3f +arm1020e_cr1_set: + .word 0x3935 __INITDATA @@ -475,7 +468,25 @@ cpu_elf_name: .type cpu_arm1020e_name, #object cpu_arm1020e_name: - .asciz "ARM1020E" + .ascii "ARM1020E" +#ifndef CONFIG_CPU_ICACHE_DISABLE + .ascii "i" +#endif +#ifndef CONFIG_CPU_DCACHE_DISABLE + .ascii "d" +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + .ascii "(wt)" +#else + .ascii "(wb)" +#endif +#endif +#ifndef CONFIG_CPU_BPREDICT_DISABLE + .ascii "B" +#endif +#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN + .ascii "RR" +#endif + .ascii "\0" .size cpu_arm1020e_name, . - cpu_arm1020e_name .align @@ -486,10 +497,6 @@ cpu_arm1020e_name: __arm1020e_proc_info: .long 0x4105a200 @ ARM 1020TE (Architecture v5TE) .long 0xff0ffff0 - .long PMD_TYPE_SECT | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \