X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmm%2Fproc-arm720.S;h=57cfa6a2f54fdd229bd11b8113325d373743c4f3;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=3bddde053bf005ff821490477d86448045ed0980;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git

diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 3bddde053..57cfa6a2f 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -124,37 +124,59 @@ ENTRY(cpu_arm720_reset)
 		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
 		mov	pc, r0
 
-		__INIT
-
-		.type	__arm710_setup, #function
-__arm710_setup:	mov	r0, #0
-		mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
-		mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
-		mcr	p15, 0, r4, c2, c0		@ load page table pointer
-		mov	r0, #0x1f			@ Domains 0, 1 = client
-		mcr	p15, 0, r0, c3, c0		@ load domain access register
-
-		mrc	p15, 0, r0, c1, c0		@ get control register
-		bic	r0, r0, #0x0e00			@ ..V. ..RS BLDP WCAM
-		orr	r0, r0, #0x0100			@ .... .... .111 .... (old)
-		orr	r0, r0, #0x003d			@ .... ..01 ..11 1101 (new)
-		mov	pc, lr				@ __ret (head-armv.S)
-		.size	__arm710_setup, . - __arm710_setup
-
-		.type	__arm720_setup, #function
-__arm720_setup:	mov	r0, #0
-		mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
-		mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
-		mcr	p15, 0, r4, c2, c0		@ load page table pointer
-		mov	r0, #0x1f			@ Domains 0, 1 = client
-		mcr	p15, 0, r0, c3, c0		@ load domain access register
-
-		mrc	p15, 0, r0, c1, c0		@ get control register
-		bic	r0, r0, #0x0e00			@ ..V. ..RS BLDP WCAM
-		orr	r0, r0, #0x2100			@ .... .... .111 .... (old)
-		orr	r0, r0, #0x003d			@ ..1. ..01 ..11 1101 (new)
-		mov	pc, lr				@ __ret (head-armv.S)
-		.size	__arm720_setup, . - __arm720_setup
+	__INIT
+
+	.type	__arm710_setup, #function
+__arm710_setup:
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
+	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
+	mrc	p15, 0, r0, c1, c0		@ get control register
+	ldr	r5, arm710_cr1_clear
+	bic	r0, r0, r5
+	ldr	r5, arm710_cr1_set
+	orr	r0, r0, r5
+	mov	pc, lr				@ __ret (head.S)
+	.size	__arm710_setup, . - __arm710_setup
+
+	/*
+	 *  R
+	 * .RVI ZFRS BLDP WCAM
+	 * .... 0001 ..11 1101
+	 * 
+	 */
+	.type	arm710_cr1_clear, #object
+	.type	arm710_cr1_set, #object
+arm710_cr1_clear:
+	.word	0x0f3f
+arm710_cr1_set:
+	.word	0x013d
+
+	.type	__arm720_setup, #function
+__arm720_setup:
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
+	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
+	mrc	p15, 0, r0, c1, c0		@ get control register
+	ldr	r5, arm720_cr1_clear
+	bic	r0, r0, r5
+	ldr	r5, arm720_cr1_set
+	orr	r0, r0, r5
+	mov	pc, lr				@ __ret (head.S)
+	.size	__arm720_setup, . - __arm720_setup
+
+	/*
+	 *  R
+	 * .RVI ZFRS BLDP WCAM
+	 * ..1. 1001 ..11 1101
+	 * 
+	 */
+	.type	arm720_cr1_clear, #object
+	.type	arm720_cr1_set, #object
+arm720_cr1_clear:
+	.word	0x2f3f
+arm720_cr1_set:
+	.word	0x213d
 
 		__INITDATA
 
@@ -206,7 +228,12 @@ cpu_arm720_name:
 __arm710_proc_info:
 		.long	0x41807100				@ cpu_val
 		.long	0xffffff00				@ cpu_mask
-		.long	0x00000c1e				@ section_mmu_flags
+		.long   PMD_TYPE_SECT | \
+			PMD_SECT_BUFFERABLE | \
+			PMD_SECT_CACHEABLE | \
+			PMD_BIT4 | \
+			PMD_SECT_AP_WRITE | \
+			PMD_SECT_AP_READ
 		b	__arm710_setup				@ cpu_flush
 		.long	cpu_arch_name				@ arch_name
 		.long	cpu_elf_name				@ elf_name
@@ -222,7 +249,12 @@ __arm710_proc_info:
 __arm720_proc_info:
 		.long	0x41807200				@ cpu_val
 		.long	0xffffff00				@ cpu_mask
-		.long	0x00000c1e				@ section_mmu_flags
+		.long   PMD_TYPE_SECT | \
+			PMD_SECT_BUFFERABLE | \
+			PMD_SECT_CACHEABLE | \
+			PMD_BIT4 | \
+			PMD_SECT_AP_WRITE | \
+			PMD_SECT_AP_READ
 		b	__arm720_setup				@ cpu_flush
 		.long	cpu_arch_name				@ arch_name
 		.long	cpu_elf_name				@ elf_name