X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmm%2Fproc-arm925.S;h=44c2c997819f522393b6b9454877fd1d79f64cba;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=917eb5e16235793f33b80921a468eb7036589009;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 917eb5e16..44c2c9978 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -9,6 +9,8 @@ * Update for Linux-2.6 and cache flush improvements * Copyright (C) 2004 Nokia Corporation by Tony Lindgren * + * hacked for non-paged-MM by Hyok S. Choi, 2004. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -48,12 +50,11 @@ */ #include -#include #include #include +#include +#include #include -#include -#include #include #include #include "proc-macros.S" @@ -122,7 +123,9 @@ ENTRY(cpu_arm925_reset) mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_MMU mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs +#endif mrc p15, 0, ip, c1, c0, 0 @ ctrl register bic ip, ip, #0x000f @ ............wcam bic ip, ip, #0x1100 @ ...i...s........ @@ -225,6 +228,19 @@ ENTRY(arm925_flush_user_cache_range) * - end - virtual end address */ ENTRY(arm925_coherent_kern_range) + /* FALLTHROUGH */ + +/* + * coherent_user_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm925_coherent_user_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry @@ -329,6 +345,7 @@ ENTRY(arm925_cache_fns) .long arm925_flush_user_cache_all .long arm925_flush_user_cache_range .long arm925_coherent_kern_range + .long arm925_coherent_user_range .long arm925_flush_kern_dcache_page .long arm925_dma_inv_range .long arm925_dma_clean_range @@ -355,6 +372,7 @@ ENTRY(cpu_arm925_dcache_clean_area) */ .align 5 ENTRY(cpu_arm925_switch_mm) +#ifdef CONFIG_MMU mov ip, #0 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache @@ -369,15 +387,17 @@ ENTRY(cpu_arm925_switch_mm) mcr p15, 0, ip, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs +#endif mov pc, lr /* - * cpu_arm925_set_pte(ptep, pte) + * cpu_arm925_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 -ENTRY(cpu_arm925_set_pte) +ENTRY(cpu_arm925_set_pte_ext) +#ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY @@ -406,6 +426,7 @@ ENTRY(cpu_arm925_set_pte) mcr p15, 0, r0, c7, c10, 1 @ clean D entry #endif mcr p15, 0, r0, c7, c10, 4 @ drain WB +#endif /* CONFIG_MMU */ mov pc, lr __INIT @@ -424,46 +445,36 @@ __arm925_setup: mov r0, #0 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 +#ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 - mcr p15, 0, r4, c2, c0 @ load page table pointer +#endif #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mov r0, #4 @ disable write-back on caches explicitly mcr p15, 7, r0, c15, c0, 0 #endif - mov r0, #0x1f @ Domains 0, 1 = client - mcr p15, 0, r0, c3, c0 @ load domain access register + adr r5, arm925_crval + ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0 @ get control register v4 -/* - * Clear out 'unwanted' bits (then put them in if we need them) - */ - @ VI ZFRS BLDP WCAM - bic r0, r0, #0x0e00 - bic r0, r0, #0x0002 - bic r0, r0, #0x000c - bic r0, r0, #0x1000 @ ...0 000. .... 000. -/* - * Turn on what we want - */ - orr r0, r0, #0x0031 - orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1 - - /* Writebuffer on */ - orr r0, r0, #0x0008 @ .... .... .... 1... - + bic r0, r0, r5 + orr r0, r0, r6 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .1.. .... .... .... -#endif -#ifndef CONFIG_CPU_DCACHE_DISABLE - orr r0, r0, #0x0004 @ .... .... .... .1.. -#endif -#ifndef CONFIG_CPU_ICACHE_DISABLE - orr r0, r0, #0x1000 @ ...1 .... .... .... #endif mov pc, lr .size __arm925_setup, . - __arm925_setup + /* + * R + * .RVI ZFRS BLDP WCAM + * .011 0001 ..11 1101 + * + */ + .type arm925_crval, #object +arm925_crval: + crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130 + __INITDATA /* @@ -479,7 +490,7 @@ arm925_processor_functions: .word cpu_arm925_do_idle .word cpu_arm925_dcache_clean_area .word cpu_arm925_switch_mm - .word cpu_arm925_set_pte + .word cpu_arm925_set_pte_ext .size arm925_processor_functions, . - arm925_processor_functions .section ".rodata" @@ -496,33 +507,25 @@ cpu_elf_name: .type cpu_arm925_name, #object cpu_arm925_name: - .ascii "ARM925T" -#ifndef CONFIG_CPU_ICACHE_DISABLE - .ascii "i" -#endif -#ifndef CONFIG_CPU_DCACHE_DISABLE - .ascii "d" -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - .ascii "(wt)" -#else - .ascii "(wb)" -#endif -#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN - .ascii "RR" -#endif -#endif - .ascii "\0" + .asciz "ARM925T" .size cpu_arm925_name, . - cpu_arm925_name .align - .section ".proc.info", #alloc, #execinstr + .section ".proc.info.init", #alloc, #execinstr .type __arm925_proc_info,#object __arm925_proc_info: .long 0x54029250 .long 0xfffffff0 - .long 0x00000c12 @ mmuflags + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ b __arm925_setup .long cpu_arch_name .long cpu_elf_name @@ -538,7 +541,14 @@ __arm925_proc_info: __arm915_proc_info: .long 0x54029150 .long 0xfffffff0 - .long 0x00000c12 @ mmuflags + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ b __arm925_setup .long cpu_arch_name .long cpu_elf_name