X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmm%2Fproc-v6.S;h=0a4ff26247b0d78f1838277a79e355a73df30bfd;hb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;hp=c22cc360180bb1bc0728dd8cf2dae19be4171f5d;hpb=a2c21200f1c81b08cb55e417b68150bba439b646;p=linux-2.6.git

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index c22cc3601..0a4ff2624 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -189,12 +189,10 @@ cpu_v6_name:
  *	- cache type register is implemented
  */
 __v6_setup:
-	mrc	p15, 0, r10, c0, c0, 1		@ read cache type register
-	tst	r10, #1 << 24			@ Harvard cache?
 	mov	r10, #0
-	mcrne	p15, 0, r10, c7, c14, 0		@ clean+invalidate D cache
-	mcrne	p15, 0, r10, c7, c5, 0		@ invalidate I cache
-	mcreq	p15, 0, r10, c7, c15, 0		@ clean+invalidate cache
+	mcr	p15, 0, r10, c7, c14, 0		@ clean+invalidate D cache
+	mcr	p15, 0, r10, c7, c5, 0		@ invalidate I cache
+	mcr	p15, 0, r10, c7, c15, 0		@ clean+invalidate cache
 	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
@@ -258,7 +256,7 @@ __v6_proc_info:
 	b	__v6_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_FAST_MULT | HWCAP_VFP
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA
 	.long	cpu_v6_name
 	.long	v6_processor_functions
 	.long	v6wbi_tlb_fns