X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Farm%2Fmm%2Fproc-v6.S;h=7b1843befb9c2deb693947e5cac5e1f5f8823d57;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=92f3ca31b7b90e46c03f05104f6e5d6300d2ce7b;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 92f3ca31b..7b1843bef 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -2,6 +2,7 @@ * linux/arch/arm/mm/proc-v6.S * * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Modified by Catalin Marinas for noMMU support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,45 +13,22 @@ #include #include #include +#include #include -#include +#include #include #include "proc-macros.S" #define D_CACHE_LINE_SIZE 32 - .macro cpsie, flags - .ifc \flags, f - .long 0xf1080040 - .exitm - .endif - .ifc \flags, i - .long 0xf1080080 - .exitm - .endif - .ifc \flags, if - .long 0xf10800c0 - .exitm - .endif - .err - .endm - - .macro cpsid, flags - .ifc \flags, f - .long 0xf10c0040 - .exitm - .endif - .ifc \flags, i - .long 0xf10c0080 - .exitm - .endif - .ifc \flags, if - .long 0xf10c00c0 - .exitm - .endif - .err - .endm +#define TTB_C (1 << 0) +#define TTB_S (1 << 1) +#define TTB_IMP (1 << 2) +#define TTB_RGN_NC (0 << 3) +#define TTB_RGN_WBWA (1 << 3) +#define TTB_RGN_WT (2 << 3) +#define TTB_RGN_WB (3 << 3) ENTRY(cpu_v6_proc_init) mov pc, lr @@ -111,25 +89,28 @@ ENTRY(cpu_v6_dcache_clean_area) * - we are not using split page tables */ ENTRY(cpu_v6_switch_mm) +#ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id #ifdef CONFIG_SMP - orr r0, r0, #2 @ set shared pgtable + orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable #endif mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB mcr p15, 0, r2, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 mcr p15, 0, r1, c13, c0, 1 @ set context ID +#endif mov pc, lr /* - * cpu_v6_set_pte(ptep, pte) + * cpu_v6_set_pte_ext(ptep, pte, ext) * * Set a level 2 translation table entry. * * - ptep - pointer to level 2 translation table entry * (hardware version is stored at -1024 bytes) * - pte - PTE value to store + * - ext - value for extended PTE bits * * Permissions: * YUWD APX AP1 AP0 SVC User @@ -141,40 +122,43 @@ ENTRY(cpu_v6_switch_mm) * 11x0 0 1 0 r/w r/o * 1111 0 1 1 r/w r/w */ -ENTRY(cpu_v6_set_pte) +ENTRY(cpu_v6_set_pte_ext) +#ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version - bic r2, r1, #0x000003f0 - bic r2, r2, #0x00000003 - orr r2, r2, #PTE_EXT_AP0 | 2 + bic r3, r1, #0x000003f0 + bic r3, r3, #0x00000003 + orr r3, r3, r2 + orr r3, r3, #PTE_EXT_AP0 | 2 tst r1, #L_PTE_WRITE tstne r1, #L_PTE_DIRTY - orreq r2, r2, #PTE_EXT_APX + orreq r3, r3, #PTE_EXT_APX tst r1, #L_PTE_USER - orrne r2, r2, #PTE_EXT_AP1 - tstne r2, #PTE_EXT_APX - bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 + orrne r3, r3, #PTE_EXT_AP1 + tstne r3, #PTE_EXT_APX + bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 tst r1, #L_PTE_YOUNG - biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK + biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK -@ tst r1, #L_PTE_EXEC -@ orreq r2, r2, #PTE_EXT_XN + tst r1, #L_PTE_EXEC + orreq r3, r3, #PTE_EXT_XN tst r1, #L_PTE_PRESENT - moveq r2, #0 + moveq r3, #0 - str r2, [r0] + str r3, [r0] mcr p15, 0, r0, c7, c10, 1 @ flush_pte +#endif mov pc, lr cpu_v6_name: - .asciz "Some Random V6 Processor" + .asciz "ARMv6-compatible processor" .align .section ".text.init", #alloc, #execinstr @@ -217,22 +201,19 @@ __v6_setup: mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache mcr p15, 0, r0, c7, c10, 4 @ drain write buffer +#ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r0, c2, c0, 2 @ TTB control register #ifdef CONFIG_SMP - orr r4, r4, #2 @ set shared pgtable + orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable #endif mcr p15, 0, r4, c2, c0, 1 @ load TTB1 -#ifdef CONFIG_VFP - mrc p15, 0, r0, c1, c0, 2 - orr r0, r0, #(0xf << 20) - mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP -#endif +#endif /* CONFIG_MMU */ + adr r5, v6_crval + ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0, 0 @ read control register - ldr r5, v6_cr1_clear @ get mask for bits to clear bic r0, r0, r5 @ clear bits them - ldr r5, v6_cr1_set @ get mask for bits to set - orr r0, r0, r5 @ set them + orr r0, r0, r6 @ set them mov pc, lr @ return to head.S:__ret /* @@ -241,12 +222,9 @@ __v6_setup: * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced * 0 110 0011 1.00 .111 1101 < we want */ - .type v6_cr1_clear, #object - .type v6_cr1_set, #object -v6_cr1_clear: - .word 0x01e0fb7f -v6_cr1_set: - .word 0x00c0387d + .type v6_crval, #object +v6_crval: + crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c .type v6_processor_functions, #object ENTRY(v6_processor_functions) @@ -257,7 +235,7 @@ ENTRY(v6_processor_functions) .word cpu_v6_do_idle .word cpu_v6_dcache_clean_area .word cpu_v6_switch_mm - .word cpu_v6_set_pte + .word cpu_v6_set_pte_ext .size v6_processor_functions, . - v6_processor_functions .type cpu_arch_name, #object @@ -285,10 +263,14 @@ __v6_proc_info: PMD_SECT_CACHEABLE | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_SECT_XN | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ b __v6_setup .long cpu_arch_name .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA .long cpu_v6_name .long v6_processor_functions .long v6wbi_tlb_fns