X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fi386%2Fkernel%2Fcpu%2Fintel.c;h=f78243feaba63dd1510ab108cd5d9c3b043a3ac4;hb=720b94a4e7548e78be55ab8fd3be4686c57dc808;hp=e04e1c9a18931f7804a52488a7f5e3b14ac3eb62;hpb=86090fcac5e27b630656fe3d963a6b80e26dac44;p=linux-2.6.git diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c index e04e1c9a1..f78243fea 100644 --- a/arch/i386/kernel/cpu/intel.c +++ b/arch/i386/kernel/cpu/intel.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "cpu.h" @@ -19,8 +20,6 @@ #include #endif -extern int trap_init_f00f_bug(void); - #ifdef CONFIG_X86_INTEL_USERCOPY /* * Alignment at which movsl is preferred for bulk memory copies. @@ -28,6 +27,15 @@ extern int trap_init_f00f_bug(void); struct movsl_mask movsl_mask; #endif +void __init early_intel_workaround(struct cpuinfo_x86 *c) +{ + if (c->x86_vendor != X86_VENDOR_INTEL) + return; + /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ + if (c->x86 == 15 && c->x86_cache_alignment == 64) + c->x86_cache_alignment = 128; +} + /* * Early probe support logic for ppro memory erratum #50 * @@ -36,42 +44,14 @@ struct movsl_mask movsl_mask; int __init ppro_with_ram_bug(void) { - char vendor_id[16]; - int ident; - - /* Must have CPUID */ - if(!have_cpuid_p()) - return 0; - if(cpuid_eax(0)<1) - return 0; - - /* Must be Intel */ - cpuid(0, &ident, - (int *)&vendor_id[0], - (int *)&vendor_id[8], - (int *)&vendor_id[4]); - - if(memcmp(vendor_id, "IntelInside", 12)) - return 0; - - ident = cpuid_eax(1); - - /* Model 6 */ - - if(((ident>>8)&15)!=6) - return 0; - - /* Pentium Pro */ - - if(((ident>>4)&15)!=1) - return 0; - - if((ident&15) < 8) - { + /* Uses data from early_cpu_detect now */ + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && + boot_cpu_data.x86 == 6 && + boot_cpu_data.x86_model == 1 && + boot_cpu_data.x86_mask < 8) { printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); return 1; } - printk(KERN_INFO "Your Pentium Pro seems ok.\n"); return 0; } @@ -109,6 +89,7 @@ static struct _cache_table cache_table[] __initdata = { 0x43, LVL_2, 512 }, { 0x44, LVL_2, 1024 }, { 0x45, LVL_2, 2048 }, + { 0x60, LVL_1_DATA, 16 }, { 0x66, LVL_1_DATA, 8 }, { 0x67, LVL_1_DATA, 16 }, { 0x68, LVL_1_DATA, 32 }, @@ -165,7 +146,7 @@ static void __init init_intel(struct cpuinfo_x86 *c) c->f00f_bug = 1; if ( !f00f_workaround_enabled ) { - trap_init_f00f_bug(); + trap_init_virtual_IDT(); printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); f00f_workaround_enabled = 1; }