X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fi386%2Fkernel%2Fio_apic.c;h=7a324e8b86f9c4b5f2cf8d9bc40a9426cbd21c0a;hb=f7f1b0f1e2fbadeab12d24236000e778aa9b1ead;hp=4bbd49692e82b7ee1b26665e8f642b5f0601bc67;hpb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;p=linux-2.6.git diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c index 4bbd49692..7a324e8b8 100644 --- a/arch/i386/kernel/io_apic.c +++ b/arch/i386/kernel/io_apic.c @@ -42,7 +42,10 @@ #include "io_ports.h" -static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED; +int (*ioapic_renumber_irq)(int ioapic, int irq); +atomic_t irq_mis_count; + +static DEFINE_SPINLOCK(ioapic_lock); /* * Is the SiS APIC rmw bug present ? @@ -185,7 +188,7 @@ static void unmask_IO_APIC_irq (unsigned int irq) spin_unlock_irqrestore(&ioapic_lock, flags); } -void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) +static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) { struct IO_APIC_route_entry entry; unsigned long flags; @@ -255,15 +258,13 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) # define Dprintk(x...) # endif -extern cpumask_t irq_affinity[NR_IRQS]; - cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS]; #define IRQBALANCE_CHECK_ARCH -999 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH; static int physical_balance = 0; -struct irq_cpu_info { +static struct irq_cpu_info { unsigned long * last_irq; unsigned long * irq_delta; unsigned long irq; @@ -274,7 +275,7 @@ struct irq_cpu_info { #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) #define IDLE_ENOUGH(cpu,now) \ - (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1)) + (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) @@ -285,7 +286,7 @@ struct irq_cpu_info { #define BALANCED_IRQ_MORE_DELTA (HZ/10) #define BALANCED_IRQ_LESS_DELTA (HZ) -long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL; +static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL; static unsigned long move(int curr_cpu, cpumask_t allowed_mask, unsigned long now, int direction) @@ -572,6 +573,7 @@ static int balanced_irq(void *unused) for ( ; ; ) { set_current_state(TASK_INTERRUPTIBLE); time_remaining = schedule_timeout(time_remaining); + try_to_freeze(PF_FREEZE); if (time_after(jiffies, prev_balance_time+balanced_irq_interval)) { do_irq_balance(); @@ -636,7 +638,7 @@ failed: return 0; } -static int __init irqbalance_disable(char *str) +int __init irqbalance_disable(char *str) { irqbalance_disabled = 1; return 0; @@ -653,7 +655,7 @@ static inline void move_irq(int irq) } } -__initcall(balanced_irq_init); +late_initcall(balanced_irq_init); #else /* !CONFIG_IRQBALANCE */ static inline void move_irq(int irq) { } @@ -683,8 +685,8 @@ void fastcall send_IPI_self(int vector) */ #define MAX_PIRQS 8 -int pirq_entries [MAX_PIRQS]; -int pirqs_enabled; +static int pirq_entries [MAX_PIRQS]; +static int pirqs_enabled; int skip_ioapic_setup; static int __init ioapic_setup(char *str) @@ -728,7 +730,7 @@ __setup("pirq=", ioapic_pirq_setup); /* * Find the IRQ entry number of a certain pin. */ -static int __init find_irq_entry(int apic, int pin, int type) +static int find_irq_entry(int apic, int pin, int type) { int i; @@ -838,7 +840,7 @@ void __init setup_ioapic_dest(void) /* * EISA Edge/Level control register, ELCR */ -static int __init EISA_ELCR(unsigned int irq) +static int EISA_ELCR(unsigned int irq) { if (irq < 16) { unsigned int port = 0x4d0 + (irq >> 3); @@ -955,7 +957,7 @@ static int __init MPBIOS_polarity(int idx) return polarity; } -static int __init MPBIOS_trigger(int idx) +static int MPBIOS_trigger(int idx) { int bus = mp_irqs[idx].mpc_srcbus; int trigger; @@ -1069,8 +1071,13 @@ static int pin_2_irq(int idx, int apic, int pin) while (i < apic) irq += nr_ioapic_registers[i++]; irq += pin; - if ((!apic) && (irq < 16)) - irq += 16; + + /* + * For MPS mode, so far only needed by ES7000 platform + */ + if (ioapic_renumber_irq) + irq = ioapic_renumber_irq(apic, irq); + break; } default: @@ -1172,7 +1179,7 @@ static inline void ioapic_register_intr(int irq, int vector, unsigned long trigg } } -void __init setup_IO_APIC_irqs(void) +static void __init setup_IO_APIC_irqs(void) { struct IO_APIC_route_entry entry; int apic, pin, idx, irq, first_notcon = 1, vector; @@ -1251,7 +1258,7 @@ void __init setup_IO_APIC_irqs(void) /* * Set up the 8259A-master output pin: */ -void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) +static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) { struct IO_APIC_route_entry entry; unsigned long flags; @@ -1445,6 +1452,8 @@ void __init print_IO_APIC(void) return; } +#if 0 + static void print_APIC_bitfield (int base) { unsigned int v; @@ -1587,6 +1596,8 @@ void /*__init*/ print_PIC(void) printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); } +#endif /* 0 */ + static void __init enable_IO_APIC(void) { union IO_APIC_reg_01 reg_01; @@ -1879,9 +1890,7 @@ static void end_level_ioapic_irq (unsigned int irq) ack_APIC_irq(); if (!(v & (1 << (i & 0x1f)))) { -#ifdef APIC_MISMATCH_DEBUG atomic_inc(&irq_mis_count); -#endif spin_lock(&ioapic_lock); __mask_and_edge_IO_APIC_irq(irq); __unmask_and_level_IO_APIC_irq(irq); @@ -2166,7 +2175,6 @@ static inline void check_timer(void) disable_8259A_irq(0); setup_nmi(); enable_8259A_irq(0); - check_nmi_watchdog(); } return; } @@ -2189,7 +2197,6 @@ static inline void check_timer(void) add_pin_to_irq(0, 0, pin2); if (nmi_watchdog == NMI_IO_APIC) { setup_nmi(); - check_nmi_watchdog(); } return; } @@ -2290,7 +2297,7 @@ struct sysfs_ioapic_data { }; static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; -static int ioapic_suspend(struct sys_device *dev, u32 state) +static int ioapic_suspend(struct sys_device *dev, pm_message_t state) { struct IO_APIC_route_entry *entry; struct sysfs_ioapic_data *data;