X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fddb5xxx%2Fddb5477%2Firq.c;h=de433cf9fb5013b7c934e0b0bafef9038842e21e;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=5f027bfa4af8f9047cfa35cea667e88826c95c16;hpb=cee37fe97739d85991964371c1f3a745c00dd236;p=linux-2.6.git diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index 5f027bfa4..de433cf9f 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c @@ -75,8 +75,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) extern void vrc5477_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base); -extern asmlinkage void ddb5477_handle_int(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; void __init arch_init_irq(void) @@ -94,7 +93,7 @@ void __init arch_init_irq(void) /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - if (mips_machtype == MACH_NEC_ROCKHOPPERII) + if (mips_machtype == MACH_NEC_ROCKHOPPERII) set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); else set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); @@ -134,10 +133,7 @@ void __init arch_init_irq(void) /* setup cascade interrupts */ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); - - /* hook up the first-level interrupt handler */ - set_except_vector(0, ddb5477_handle_int); + setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); } u8 i8259_interrupt_ack(void) @@ -159,7 +155,7 @@ u8 i8259_interrupt_ack(void) * the first level int-handler will jump here if it is a vrc5477 irq */ #define NUM_5477_IRQS 32 -asmlinkage void +static void vrc5477_irq_dispatch(struct pt_regs *regs) { u32 intStatus; @@ -197,3 +193,21 @@ vrc5477_irq_dispatch(struct pt_regs *regs) } } } + +#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6) + +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP7) + do_IRQ(CPU_IRQ_BASE + 7, regs); + else if (pending & VR5477INTS) + vrc5477_irq_dispatch(regs); + else if (pending & STATUSF_IP0) + do_IRQ(CPU_IRQ_BASE, regs); + else if (pending & STATUSF_IP1) + do_IRQ(CPU_IRQ_BASE + 1, regs); + else + spurious_interrupt(regs); +}