X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fgt64120%2Fmomenco_ocelot%2Fsetup.c;h=d610f8c17c819b54547db0b8ef809be67ec6eeef;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=58457bca98dcc87c5084b78534146ebe70fae1f8;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git

diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 58457bca9..d610f8c17 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -304,7 +304,7 @@ static void __init momenco_ocelot_setup(void)
 	}
 
 	/* Fix up the DiskOnChip mapping */
-	GT_WRITE(0x468, 0xfef73);
+	GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
 }
 
 early_initcall(momenco_ocelot_setup);
@@ -322,8 +322,8 @@ static void __init setup_l3cache(unsigned long size)
 	printk("Enabling L3 cache...");
 
 	/* Enable the L3 cache in the GT64120A's CPU Configuration register */
-	tmp =  GT_READ(0);
-	GT_WRITE(0, tmp | (1<<14));
+	tmp = GT_READ(GT_CPU_OFS);
+	GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
 
 	/* Enable the L3 cache in the CPU */
 	set_c0_config(1<<12 /* CONF_TE */);