X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fkernel%2Fcpu-probe.c;h=8c2c359a05f413bd089a8eb40cf64781ac8bb89a;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=4bb84958231410b6b644f0fe9f692063dab872a5;hpb=cee37fe97739d85991964371c1f3a745c00dd236;p=linux-2.6.git diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4bb849582..8c2c359a0 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2,9 +2,9 @@ * Processor capabilities determination functions. * * Copyright (C) xxxx the Anonymous - * Copyright (C) 2003 Maciej W. Rozycki - * Copyright (C) 1994 - 2003 Ralf Baechle - * Copyright (C) 2001 MIPS Inc. + * Copyright (C) 1994 - 2006 Ralf Baechle + * Copyright (C) 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2001, 2004 MIPS Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -17,7 +17,6 @@ #include #include -#include #include #include #include @@ -51,36 +50,48 @@ static void r4k_wait(void) ".set\tmips0"); } -/* - * The Au1xxx wait is available only if we run CONFIG_PM and - * the timer setup found we had a 32KHz counter available. - * There are still problems with functions that may call au1k_wait - * directly, but that will be discovered pretty quickly. - */ -extern void (*au1k_wait_ptr)(void); +/* The Au1xxx wait is available only if using 32khz counter or + * external timer source, but specifically not CP0 Counter. */ +int allow_au1k_wait; -void au1k_wait(void) +static void au1k_wait(void) { -#ifdef CONFIG_PM /* using the wait instruction makes CP0 counter unusable */ - __asm__(".set\tmips3\n\t" + __asm__(".set mips3\n\t" + "cache 0x14, 0(%0)\n\t" + "cache 0x14, 32(%0)\n\t" + "sync\n\t" + "nop\n\t" "wait\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" - ".set\tmips0"); -#else - __asm__("nop\n\t" - "nop"); -#endif + ".set mips0\n\t" + : : "r" (au1k_wait)); } +static int __initdata nowait = 0; + +int __init wait_disable(char *s) +{ + nowait = 1; + + return 1; +} + +__setup("nowait", wait_disable); + static inline void check_wait(void) { struct cpuinfo_mips *c = ¤t_cpu_data; printk("Checking for 'wait' instruction... "); + if (nowait) { + printk (" disabled.\n"); + return; + } + switch (c->cputype) { case CPU_R3081: case CPU_R3081E: @@ -109,22 +120,23 @@ static inline void check_wait(void) /* case CPU_20KC:*/ case CPU_24K: case CPU_25KF: + case CPU_34K: + case CPU_74K: + case CPU_PR4450: cpu_wait = r4k_wait; printk(" available.\n"); break; -#ifdef CONFIG_PM case CPU_AU1000: case CPU_AU1100: case CPU_AU1500: - if (au1k_wait_ptr != NULL) { - cpu_wait = au1k_wait_ptr; + case CPU_AU1550: + case CPU_AU1200: + if (allow_au1k_wait) { + cpu_wait = au1k_wait; printk(" available.\n"); - } - else { + } else printk(" unavailable.\n"); - } break; -#endif default: printk(" unavailable.\n"); break; @@ -180,7 +192,7 @@ static inline int __cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } -#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ +#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) static inline void cpu_probe_legacy(struct cpuinfo_mips *c) @@ -189,7 +201,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R2000: c->cputype = CPU_R2000; c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -203,7 +216,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) else c->cputype = CPU_R3000; c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -229,15 +243,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_VR41XX: switch (c->processor_id & 0xf0) { -#ifndef CONFIG_VR4181 case PRID_REV_VR4111: c->cputype = CPU_VR4111; break; -#else - case PRID_REV_VR4181: - c->cputype = CPU_VR4181; - break; -#endif case PRID_REV_VR4121: c->cputype = CPU_VR4121; break; @@ -272,7 +280,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R4600: c->cputype = CPU_R4600; c->isa_level = MIPS_CPU_ISA_III; - c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; c->tlbsize = 48; break; #if 0 @@ -283,7 +292,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) * for documentation. Commented out because it shares * it's c0_prid id number with the TX3900. */ - c->cputype = CPU_R4650; + c->cputype = CPU_R4650; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; @@ -291,7 +300,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) #endif case PRID_IMP_TX39: c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB; + c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; @@ -409,7 +418,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R10000: c->cputype = CPU_R10000; c->isa_level = MIPS_CPU_ISA_IV; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -418,7 +427,16 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R12000: c->cputype = CPU_R12000; c->isa_level = MIPS_CPU_ISA_IV; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_COUNTER | MIPS_CPU_WATCH | + MIPS_CPU_LLSC; + c->tlbsize = 64; + break; + case PRID_IMP_R14000: + c->cputype = CPU_R14000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -427,80 +445,179 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) } } -static inline void decode_config1(struct cpuinfo_mips *c) +static char unknown_isa[] __initdata = KERN_ERR \ + "Unsupported ISA type, c0.config0: %d."; + +static inline unsigned int decode_config0(struct cpuinfo_mips *c) { - unsigned long config0 = read_c0_config(); - unsigned long config1; + unsigned int config0; + int isa; + + config0 = read_c0_config(); - if ((config0 & (1 << 31)) == 0) - return; /* actually wort a panic() */ + if (((config0 & MIPS_CONF_MT) >> 7) == 1) + c->options |= MIPS_CPU_TLB; + isa = (config0 & MIPS_CONF_AT) >> 13; + switch (isa) { + case 0: + switch ((config0 >> 10) & 7) { + case 0: + c->isa_level = MIPS_CPU_ISA_M32R1; + break; + case 1: + c->isa_level = MIPS_CPU_ISA_M32R2; + break; + default: + goto unknown; + } + break; + case 2: + switch ((config0 >> 10) & 7) { + case 0: + c->isa_level = MIPS_CPU_ISA_M64R1; + break; + case 1: + c->isa_level = MIPS_CPU_ISA_M64R2; + break; + default: + goto unknown; + } + break; + default: + goto unknown; + } + + return config0 & MIPS_CONF_M; + +unknown: + panic(unknown_isa, config0); +} + +static inline unsigned int decode_config1(struct cpuinfo_mips *c) +{ + unsigned int config1; - /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_LLSC | MIPS_CPU_MCHECK; config1 = read_c0_config1(); - if (config1 & (1 << 3)) + + if (config1 & MIPS_CONF1_MD) + c->ases |= MIPS_ASE_MDMX; + if (config1 & MIPS_CONF1_WR) c->options |= MIPS_CPU_WATCH; - if (config1 & (1 << 2)) - c->options |= MIPS_CPU_MIPS16; - if (config1 & (1 << 1)) + if (config1 & MIPS_CONF1_CA) + c->ases |= MIPS_ASE_MIPS16; + if (config1 & MIPS_CONF1_EP) c->options |= MIPS_CPU_EJTAG; - if (config1 & 1) { + if (config1 & MIPS_CONF1_FP) { c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_32FPR; } + if (cpu_has_tlb) + c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; + + return config1 & MIPS_CONF_M; +} + +static inline unsigned int decode_config2(struct cpuinfo_mips *c) +{ + unsigned int config2; + + config2 = read_c0_config2(); + + if (config2 & MIPS_CONF2_SL) + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return config2 & MIPS_CONF_M; +} + +static inline unsigned int decode_config3(struct cpuinfo_mips *c) +{ + unsigned int config3; + + config3 = read_c0_config3(); + + if (config3 & MIPS_CONF3_SM) + c->ases |= MIPS_ASE_SMARTMIPS; + if (config3 & MIPS_CONF3_DSP) + c->ases |= MIPS_ASE_DSP; + if (config3 & MIPS_CONF3_VINT) + c->options |= MIPS_CPU_VINT; + if (config3 & MIPS_CONF3_VEIC) + c->options |= MIPS_CPU_VEIC; + if (config3 & MIPS_CONF3_MT) + c->ases |= MIPS_ASE_MIPSMT; + + return config3 & MIPS_CONF_M; +} + +static inline void decode_configs(struct cpuinfo_mips *c) +{ + /* MIPS32 or MIPS64 compliant CPU. */ + c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; + c->scache.flags = MIPS_CACHE_NOT_PRESENT; - c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + /* Read Config registers. */ + if (!decode_config0(c)) + return; /* actually worth a panic() */ + if (!decode_config1(c)) + return; + if (!decode_config2(c)) + return; + if (!decode_config3(c)) + return; } static inline void cpu_probe_mips(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KEC: c->cputype = CPU_4KEC; - c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KECR2: + c->cputype = CPU_4KEC; break; case PRID_IMP_4KSC: + case PRID_IMP_4KSD: c->cputype = CPU_4KSC; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; - c->isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; - c->isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_24K: + case PRID_IMP_24KE: c->cputype = CPU_24K; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; - c->isa_level = MIPS_CPU_ISA_M64; /* Probe for L2 cache */ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; + case PRID_IMP_34K: + c->cputype = CPU_34K; + break; + case PRID_IMP_74K: + c->cputype = CPU_74K; + break; } } static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: switch ((c->processor_id >> 24) & 0xff) { case 0: - c->cputype = CPU_AU1000; + c->cputype = CPU_AU1000; break; case 1: c->cputype = CPU_AU1500; @@ -511,50 +628,69 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) case 3: c->cputype = CPU_AU1550; break; + case 4: + c->cputype = CPU_AU1200; + break; default: panic("Unknown Au Core!"); break; } - c->isa_level = MIPS_CPU_ISA_M32; break; } } static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); + + /* + * For historical reasons the SB1 comes with it's own variant of + * cache code which eventually will be folded into c-r4k.c. Until + * then we pretend it's got it's own cache architecture. + */ + c->options &= ~MIPS_CPU_4K_CACHE; + c->options |= MIPS_CPU_SB1_CACHE; + switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; - c->isa_level = MIPS_CPU_ISA_M64; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | - MIPS_CPU_WATCH | MIPS_CPU_LLSC; -#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS /* FPU in pass1 is known to have issues. */ - c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; -#endif + if ((c->processor_id & 0xff) < 0x02) + c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); + break; + case PRID_IMP_SB1A: + c->cputype = CPU_SB1A; break; } } static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; - c->isa_level = MIPS_CPU_ISA_M64; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_FPU | - MIPS_CPU_COUNTER | MIPS_CPU_MCHECK; c->scache.ways = 8; c->tlbsize = 64; break; } } +static inline void cpu_probe_philips(struct cpuinfo_mips *c) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_PR4450: + c->cputype = CPU_PR4450; + c->isa_level = MIPS_CPU_ISA_M32R1; + break; + default: + panic("Unknown Philips Core!"); /* REVISIT: die? */ + break; + } +} + + __init void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -577,15 +713,26 @@ __init void cpu_probe(void) case PRID_COMP_SIBYTE: cpu_probe_sibyte(c); break; - case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; + case PRID_COMP_PHILIPS: + cpu_probe_philips(c); + break; default: c->cputype = CPU_UNKNOWN; } - if (c->options & MIPS_CPU_FPU) + if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); + + if (c->isa_level == MIPS_CPU_ISA_M32R1 || + c->isa_level == MIPS_CPU_ISA_M32R2 || + c->isa_level == MIPS_CPU_ISA_M64R1 || + c->isa_level == MIPS_CPU_ISA_M64R2) { + if (c->fpu_id & MIPS_FPIR_3D) + c->ases |= MIPS_ASE_MIPS3D; + } + } } __init void cpu_report(void)