X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fmips-boards%2Fgeneric%2Ftime.c;h=a3c3a1d462b272f39900d9c9910ac1f1d8bde455;hb=refs%2Fremotes%2Fvserver;hp=93f3bf2c2b22364217e4fe9ae925b1e36b8470e0;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 93f3bf2c2..a3c3a1d46 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -19,7 +19,6 @@ */ #include -#include #include #include #include @@ -30,7 +29,7 @@ #include #include -#include +#include #include #include #include @@ -41,8 +40,16 @@ #include #include + +#ifdef CONFIG_MIPS_ATLAS +#include +#endif +#ifdef CONFIG_MIPS_MALTA #include -#include +#endif +#ifdef CONFIG_MIPS_SEAD +#include +#endif unsigned long cpu_khz; @@ -50,16 +57,23 @@ unsigned long cpu_khz; static char display_string[] = " LINUX ON ATLAS "; #endif #if defined(CONFIG_MIPS_MALTA) +#if defined(CONFIG_MIPS_MT_SMTC) +static char display_string[] = " SMTC LINUX ON MALTA "; +#else static char display_string[] = " LINUX ON MALTA "; +#endif /* CONFIG_MIPS_MT_SMTC */ #endif #if defined(CONFIG_MIPS_SEAD) static char display_string[] = " LINUX ON SEAD "; #endif -static unsigned int display_count = 0; +static unsigned int display_count; #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) -static unsigned int timer_tick_count=0; +#define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR) + +static unsigned int timer_tick_count; static int mips_cpu_timer_irq; +extern void smtc_timer_broadcast(int); static inline void scroll_display_message(void) { @@ -70,20 +84,76 @@ static inline void scroll_display_message(void) } } -static void mips_timer_dispatch (struct pt_regs *regs) +static void mips_timer_dispatch(void) { - do_IRQ (mips_cpu_timer_irq, regs); + do_IRQ(mips_cpu_timer_irq); } -extern int null_perf_irq(struct pt_regs *regs); +/* + * Redeclare until I get around mopping the timer code insanity on MIPS. + */ +extern int null_perf_irq(void); -extern int (*perf_irq)(struct pt_regs *regs); +extern int (*perf_irq)(void); -irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +irqreturn_t mips_timer_interrupt(int irq, void *dev_id) { - int r2 = cpu_has_mips_r2; int cpu = smp_processor_id(); +#ifdef CONFIG_MIPS_MT_SMTC + /* + * In an SMTC system, one Count/Compare set exists per VPE. + * Which TC within a VPE gets the interrupt is essentially + * random - we only know that it shouldn't be one with + * IXMT set. Whichever TC gets the interrupt needs to + * send special interprocessor interrupts to the other + * TCs to make sure that they schedule, etc. + * + * That code is specific to the SMTC kernel, not to + * the a particular platform, so it's invoked from + * the general MIPS timer_interrupt routine. + */ + + int vpflags; + + /* + * We could be here due to timer interrupt, + * perf counter overflow, or both. + */ + if (read_c0_cause() & (1 << 26)) + perf_irq(); + + if (read_c0_cause() & (1 << 30)) { + /* If timer interrupt, make it de-assert */ + write_c0_compare (read_c0_count() - 1); + /* + * DVPE is necessary so long as cross-VPE interrupts + * are done via read-modify-write of Cause register. + */ + vpflags = dvpe(); + clear_c0_cause(CPUCTR_IMASKBIT); + evpe(vpflags); + /* + * There are things we only want to do once per tick + * in an "MP" system. One TC of each VPE will take + * the actual timer interrupt. The others will get + * timer broadcast IPIs. We use whoever it is that takes + * the tick on VPE 0 to run the full timer_interrupt(). + */ + if (cpu_data[cpu].vpe_id == 0) { + timer_interrupt(irq, NULL); + smtc_timer_broadcast(cpu_data[cpu].vpe_id); + scroll_display_message(); + } else { + write_c0_compare(read_c0_count() + + (mips_hpt_frequency/HZ)); + local_timer_interrupt(irq, dev_id); + smtc_timer_broadcast(cpu_data[cpu].vpe_id); + } + } +#else /* CONFIG_MIPS_MT_SMTC */ + int r2 = cpu_has_mips_r2; + if (cpu == 0) { /* * CPU 0 handles the global timer interrupt job and process @@ -91,12 +161,12 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * timer int. */ if (!r2 || (read_c0_cause() & (1 << 26))) - if (perf_irq(regs)) + if (perf_irq()) goto out; /* we keep interrupt disabled all the time */ if (!r2 || (read_c0_cause() & (1 << 30))) - timer_interrupt(irq, NULL, regs); + timer_interrupt(irq, NULL); scroll_display_message(); } else { @@ -107,26 +177,27 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * More support needs to be added to kernel/time for * counter/timer interrupts on multiple CPU's */ - write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ)); + write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); + /* - * other CPUs should do profiling and process accounting + * Other CPUs should do profiling and process accounting */ - local_timer_interrupt (irq, dev_id, regs); + local_timer_interrupt(irq, dev_id); } - out: +#endif /* CONFIG_MIPS_MT_SMTC */ return IRQ_HANDLED; } /* - * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect */ static unsigned int __init estimate_cpu_frequency(void) { unsigned int prid = read_c0_prid() & 0xffff00; unsigned int count; -#ifdef CONFIG_MIPS_SEAD +#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) /* * The SEAD board doesn't have a real time clock, so we can't * really calculate the timer frequency @@ -140,7 +211,8 @@ static unsigned int __init estimate_cpu_frequency(void) count = 6000000; #endif #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) - unsigned int flags; + unsigned long flags; + unsigned int start; local_irq_save(flags); @@ -149,13 +221,13 @@ static unsigned int __init estimate_cpu_frequency(void) while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); /* Start r4k counter. */ - write_c0_count(0); + start = read_c0_count(); /* Read counter exactly on falling edge of update flag */ while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - count = read_c0_count(); + count = read_c0_count() - start; /* restore interrupts */ local_irq_restore(flags); @@ -179,9 +251,7 @@ unsigned long __init mips_rtc_get_time(void) void __init mips_time_init(void) { - unsigned int est_freq, flags; - - local_irq_save(flags); + unsigned int est_freq; /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); @@ -192,17 +262,17 @@ void __init mips_time_init(void) (est_freq%1000000)*100/1000000); cpu_khz = est_freq / 1000; - - local_irq_restore(flags); } -void __init mips_timer_setup(struct irqaction *irq) +void __init plat_timer_setup(struct irqaction *irq) { +#ifdef MSC01E_INT_BASE if (cpu_has_veic) { set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - } - else { + } else +#endif + { if (cpu_has_vint) set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; @@ -211,7 +281,11 @@ void __init mips_timer_setup(struct irqaction *irq) /* we are using the cpu counter for timer interrupts */ irq->handler = mips_timer_interrupt; /* we use our own handler */ +#ifdef CONFIG_MIPS_MT_SMTC + setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT); +#else setup_irq(mips_cpu_timer_irq, irq); +#endif /* CONFIG_MIPS_MT_SMTC */ #ifdef CONFIG_SMP /* irq_desc(riptor) is a global resource, when the interrupt overlaps @@ -219,6 +293,7 @@ void __init mips_timer_setup(struct irqaction *irq) The effect is that the int remains disabled on the second cpu. Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; + set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */