X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fmm%2Fc-r4k.c;h=a761f99bcf98f21eaaa2b9f274b3f920c5b6cca4;hb=987b0145d94eecf292d8b301228356f44611ab7c;hp=4a43924cd4fccd1f3415a79bc0562d20420632c8;hpb=f7ed79d23a47594e7834d66a8f14449796d4f3e6;p=linux-2.6.git diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4a43924cd..a761f99bc 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -29,27 +29,6 @@ #include #include /* for run_uncached() */ - -/* - * Special Variant of smp_call_function for use by cache functions: - * - * o No return value - * o collapses to normal function call on UP kernels - * o collapses to normal function call on systems with a single shared - * primary cache. - */ -static inline void r4k_on_each_cpu(void (*func) (void *info), void *info, - int retry, int wait) -{ - preempt_disable(); - -#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) - smp_call_function(func, info, retry, wait); -#endif - func(info); - preempt_enable(); -} - /* * Must die. */ @@ -320,7 +299,7 @@ static void r4k_flush_cache_all(void) if (!cpu_has_dc_aliases) return; - r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); + on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); } static inline void local_r4k___flush_cache_all(void * args) @@ -335,14 +314,13 @@ static inline void local_r4k___flush_cache_all(void * args) case CPU_R4400MC: case CPU_R10000: case CPU_R12000: - case CPU_R14000: r4k_blast_scache(); } } static void r4k___flush_cache_all(void) { - r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); + on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); } static inline void local_r4k_flush_cache_range(void * args) @@ -363,7 +341,7 @@ static inline void local_r4k_flush_cache_range(void * args) static void r4k_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); + on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); } static inline void local_r4k_flush_cache_mm(void * args) @@ -392,7 +370,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm) if (!cpu_has_dc_aliases) return; - r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); + on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); } struct flush_cache_page_args { @@ -483,7 +461,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma, args.addr = addr; args.pfn = pfn; - r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); + on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); } static inline void local_r4k_flush_data_cache_page(void * addr) @@ -493,7 +471,7 @@ static inline void local_r4k_flush_data_cache_page(void * addr) static void r4k_flush_data_cache_page(unsigned long addr) { - r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); + on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); } struct flush_icache_range_args { @@ -536,7 +514,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end) args.start = start; args.end = end; - r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); + on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); instruction_hazard(); } @@ -612,7 +590,7 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma, args.vma = vma; args.page = page; - r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); + on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); } @@ -711,7 +689,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg) static void r4k_flush_cache_sigtramp(unsigned long addr) { - r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); + on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); } static void r4k_flush_icache_all(void) @@ -772,12 +750,12 @@ static void __init probe_pcache(void) icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); c->icache.linesz = 16 << ((config & CONF_IB) >> 5); c->icache.ways = 2; - c->icache.waybit = __ffs(icache_size/2); + c->icache.waybit = ffs(icache_size/2) - 1; dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); c->dcache.ways = 2; - c->dcache.waybit= __ffs(dcache_size/2); + c->dcache.waybit= ffs(dcache_size/2) - 1; c->options |= MIPS_CPU_CACHE_CDEX_P; break; @@ -809,7 +787,6 @@ static void __init probe_pcache(void) c->dcache.waybit = 0; c->options |= MIPS_CPU_CACHE_CDEX_P; - c->options |= MIPS_CPU_PREFETCH; break; case CPU_R4000PC: @@ -834,7 +811,6 @@ static void __init probe_pcache(void) case CPU_R10000: case CPU_R12000: - case CPU_R14000: icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); c->icache.linesz = 64; c->icache.ways = 2; @@ -861,12 +837,12 @@ static void __init probe_pcache(void) icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); c->icache.linesz = 16 << ((config & CONF_IB) >> 5); c->icache.ways = 2; - c->icache.waybit = __ffs(icache_size/2); + c->icache.waybit = ffs(icache_size/2) - 1; dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); c->dcache.ways = 2; - c->dcache.waybit = __ffs(dcache_size/2); + c->dcache.waybit = ffs(dcache_size/2) - 1; c->options |= MIPS_CPU_CACHE_CDEX_P; break; @@ -897,12 +873,12 @@ static void __init probe_pcache(void) icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); c->icache.linesz = 16 << ((config & CONF_IB) >> 5); c->icache.ways = 4; - c->icache.waybit = __ffs(icache_size / c->icache.ways); + c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); c->dcache.ways = 4; - c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); + c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR) c->options |= MIPS_CPU_CACHE_CDEX_P; @@ -930,7 +906,7 @@ static void __init probe_pcache(void) icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; - c->icache.waybit = __ffs(icache_size/c->icache.ways); + c->icache.waybit = ffs(icache_size/c->icache.ways) - 1; if (config & 0x8) /* VI bit */ c->icache.flags |= MIPS_CACHE_VTAG; @@ -950,7 +926,7 @@ static void __init probe_pcache(void) dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; - c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); + c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1; c->options |= MIPS_CPU_PREFETCH; break; @@ -988,11 +964,9 @@ static void __init probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; case CPU_R10000: case CPU_R12000: - case CPU_R14000: case CPU_SB1: break; case CPU_24K: - case CPU_34K: if (!(read_c0_config7() & (1 << 16))) default: if (c->dcache.waysize > PAGE_SIZE) @@ -1116,7 +1090,6 @@ static void __init setup_scache(void) case CPU_R10000: case CPU_R12000: - case CPU_R14000: scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); c->scache.linesz = 64 << ((config >> 13) & 1); c->scache.ways = 2; @@ -1161,31 +1134,6 @@ static void __init setup_scache(void) c->options |= MIPS_CPU_SUBSET_CACHES; } -void au1x00_fixup_config_od(void) -{ - /* - * c0_config.od (bit 19) was write only (and read as 0) - * on the early revisions of Alchemy SOCs. It disables the bus - * transaction overlapping and needs to be set to fix various errata. - */ - switch (read_c0_prid()) { - case 0x00030100: /* Au1000 DA */ - case 0x00030201: /* Au1000 HA */ - case 0x00030202: /* Au1000 HB */ - case 0x01030200: /* Au1500 AB */ - /* - * Au1100 errata actually keeps silence about this bit, so we set it - * just in case for those revisions that require it to be set according - * to arch/mips/au1000/common/cputable.c - */ - case 0x02030200: /* Au1100 AB */ - case 0x02030201: /* Au1100 BA */ - case 0x02030202: /* Au1100 BC */ - set_c0_config(1 << 19); - break; - } -} - static inline void coherency_setup(void) { change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); @@ -1206,15 +1154,6 @@ static inline void coherency_setup(void) case CPU_R4400MC: clear_c0_config(CONF_CU); break; - /* - * We need to catch the ealry Alchemy SOCs with - * the write-only co_config.od bit and set it back to one... - */ - case CPU_AU1000: /* rev. DA, HA, HB */ - case CPU_AU1100: /* rev. AB, BA, BC ?? */ - case CPU_AU1500: /* rev. AB */ - au1x00_fixup_config_od(); - break; } } @@ -1259,7 +1198,6 @@ void __init r4k_cache_init(void) flush_cache_sigtramp = r4k_flush_cache_sigtramp; flush_icache_all = r4k_flush_icache_all; - local_flush_data_cache_page = local_r4k_flush_data_cache_page; flush_data_cache_page = r4k_flush_data_cache_page; flush_icache_range = r4k_flush_icache_range;