X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fmm%2Ftlb-r4k.c;h=91fee06881f9d2fa16d72de6812f365137fe5f4b;hb=6f71f83334a552167ccbbd42fe5dd979428c89e4;hp=59d38bc05b6911f9137adcee46befa41065c6c08;hpb=8d40237c730b8be87c1b80a5d96b9c603fefa829;p=linux-2.6.git

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 59d38bc05..91fee0688 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -19,7 +19,12 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 
-extern void build_tlb_refill_handler(void);
+extern void except_vec0_generic(void);
+extern void except_vec0_nevada(void);
+extern void except_vec0_r4000(void);
+extern void except_vec0_r4600(void);
+extern void except_vec1_generic(void);
+extern void except_vec1_r4k(void);
 
 /* CP0 hazard avoidance. */
 #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
@@ -250,14 +255,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 	idx = read_c0_index();
 	ptep = pte_offset_map(pmdp, address);
 
- #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
- 	write_c0_entrylo0(ptep->pte_high);
- 	ptep++;
- 	write_c0_entrylo1(ptep->pte_high);
-#else
-  	write_c0_entrylo0(pte_val(*ptep++) >> 6);
-  	write_c0_entrylo1(pte_val(*ptep) >> 6);
-#endif
+	write_c0_entrylo0(pte_val(*ptep++) >> 6);
+	write_c0_entrylo1(pte_val(*ptep) >> 6);
 	write_c0_entryhi(address | pid);
 	mtc0_tlbw_hazard();
 	if (idx < 0)
@@ -415,5 +414,19 @@ void __init tlb_init(void)
 	temp_tlb_entry = current_cpu_data.tlbsize - 1;
 	local_flush_tlb_all();
 
-	build_tlb_refill_handler();
+#ifdef CONFIG_MIPS32
+	if (current_cpu_data.cputype == CPU_NEVADA)
+		memcpy((void *)KSEG0, &except_vec0_nevada, 0x80);
+	else if (current_cpu_data.cputype == CPU_R4600)
+		memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
+	else
+		memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
+	memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80);
+	flush_icache_range(KSEG0, KSEG0 + 0x100);
+#endif
+#ifdef CONFIG_MIPS64
+	memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80);
+	memcpy((void *)(CKSEG0 + 0x80), except_vec1_r4k, 0x80);
+	flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100);
+#endif
 }