X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fmomentum%2Focelot_g%2Fgt-irq.c;h=e5576bd50fa9e3f7e818cac510f803cd559d1ad1;hb=a2f44b27303a5353859d77a3e96a1d3f33f56ab7;hp=3afe3273921c57217188b31c180e8a338536b521;hpb=daddc0d38b3571bed170afa273a49a0eba090c1e;p=linux-2.6.git diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c index 3afe32739..e5576bd50 100644 --- a/arch/mips/momentum/ocelot_g/gt-irq.c +++ b/arch/mips/momentum/ocelot_g/gt-irq.c @@ -14,11 +14,10 @@ #include #include #include -#include #include #include +#include #include -#include "gt64240.h" unsigned long bus_clock; @@ -28,7 +27,7 @@ unsigned long bus_clock; * be handled and ack'ed differently than other MIPS interrupts. */ -#if CURRENTLY_UNUSED +#if 0 struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); @@ -58,7 +57,7 @@ void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) * bit_num - Indicates which bit number in the cause register * * Outputs : - * 1 if succesful, 0 if failure + * 1 if successful, 0 if failure */ int enable_galileo_irq(int int_cause, int bit_num) { @@ -82,7 +81,7 @@ int enable_galileo_irq(int int_cause, int bit_num) * bit_num - Indicates which bit number in the cause register * * Outputs : - * 1 if succesful, 0 if failure + * 1 if successful, 0 if failure */ int disable_galileo_irq(int int_cause, int bit_num) { @@ -96,7 +95,7 @@ int disable_galileo_irq(int int_cause, int bit_num) return 0; return 1; } -#endif /* UNUSED */ +#endif /* 0 */ /* * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#. @@ -108,123 +107,44 @@ int disable_galileo_irq(int int_cause, int bit_num) * we keep this particular structure in the function. */ -static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs) +static irqreturn_t gt64240_p0int_irq(int irq, void *dev) { uint32_t irq_src, irq_src_mask; int handled; /* get the low interrupt cause register */ - GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src); + irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER); /* get the mask register for this pin */ - GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask); + irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW); /* mask off only the interrupts we're interested in */ irq_src = irq_src & irq_src_mask; - handled = 0; + handled = IRQ_NONE; /* Check for timer interrupt */ if (irq_src & 0x00000100) { - handled = 1; + handled = IRQ_HANDLED; irq_src &= ~0x00000100; /* Clear any pending cause bits */ - GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); + MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); /* handle the timer call */ - do_timer(regs); - } - - if (irq_src) { - printk(KERN_INFO - "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", - irq_src); - } -} - -/* - * Interrupt handler for interrupts coming from the Galileo chip. - * It could be built in ethernet ports etc... - */ -static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs) -{ - unsigned int irq_src, int_high_src, irq_src_mask, - int_high_src_mask; - int handled; - -#if 0 - GT_READ(GT_INTRCAUSE_OFS, &irq_src); - GT_READ(GT_INTRMASK_OFS, &irq_src_mask); - GT_READ(GT_HINTRCAUSE_OFS, &int_high_src); - GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask); + do_timer(1); +#ifndef CONFIG_SMP + update_process_times(user_mode(get_irq_regs())); #endif - irq_src = irq_src & irq_src_mask; - int_high_src = int_high_src & int_high_src_mask; - - handled = 0; - - /* Execute all interrupt handlers */ - /* Check for timer interrupt */ - if (irq_src & 0x00000800) { - handled = 1; - irq_src &= ~0x00000800; - // RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8); - do_timer(regs); } if (irq_src) { printk(KERN_INFO - "Other Galileo interrupt received irq_src %x\n", + "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", irq_src); -#if CURRENTLY_UNUSED - for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) { - if (irq_src & (1 << count)) { - if (irq_handlers[INT_CAUSE_MAIN][count]. - routine) { - queue_task(&irq_handlers - [INT_CAUSE_MAIN][count], - &tq_immediate); - mark_bh(IMMEDIATE_BH); - handled = 1; - } - } - } -#endif /* UNUSED */ - } -#if 0 - GT_WRITE(GT_INTRCAUSE_OFS, 0); - GT_WRITE(GT_HINTRCAUSE_OFS, 0); -#endif - -#undef GALILEO_I2O -#ifdef GALILEO_I2O - /* - * Future I2O support. We currently attach I2O interrupt handlers to - * the Galileo interrupt (int 4) and handle them in do_IRQ. - */ - if (isInBoundDoorBellInterruptSet()) { - printk(KERN_INFO "I2O doorbell interrupt received.\n"); - handled = 1; } - if (isInBoundPostQueueInterruptSet()) { - printk(KERN_INFO "I2O Queue interrupt received.\n"); - handled = 1; - } - - /* - * This normally would be outside of the ifdef, but since we're - * handling I2O outside of this handler, this printk shows up every - * time we get a valid I2O interrupt. So turn this off for now. - */ - if (handled == 0) { - if (counter < 50) { - printk("Spurious Galileo interrupt...\n"); - counter++; - } - } -#endif + return handled; } /* @@ -238,14 +158,13 @@ static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs) */ void gt64240_time_init(void) { - extern irq_desc_t irq_desc[NR_IRQS]; static struct irqaction timer; /* Stop the timer -- we'll use timer #0 */ - GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); + MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); /* Load timer value for 100 Hz */ - GT_WRITE(TIMER_COUNTER0, bus_clock / 100); + MV_WRITE(TIMER_COUNTER0, bus_clock / 100); /* * Create the IRQ structure entry for the timer. Since we're too early @@ -253,31 +172,31 @@ void gt64240_time_init(void) * the values to the correct interrupt line. */ timer.handler = >64240_p0int_irq; - timer.flags = SA_SHIRQ | SA_INTERRUPT; + timer.flags = IRQF_SHARED | IRQF_DISABLED; timer.name = "timer"; timer.dev_id = NULL; timer.next = NULL; - timer.mask = 0; + timer.mask = CPU_MASK_NONE; irq_desc[6].action = &timer; enable_irq(6); /* Clear any pending cause bits */ - GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); + MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); /* Enable the interrupt for timer 0 */ - GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); + MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); /* Enable the timer interrupt for GT-64240 pin P0_INT# */ - GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); + MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); /* Configure and start the timer */ - GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); + MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); } void gt64240_irq_init(void) { -#if CURRENTLY_UNUSED +#if 0 int i, j; /* Reset irq handlers pointers to NULL */ @@ -289,5 +208,5 @@ void gt64240_irq_init(void) irq_handlers[i][j].data = NULL; } } -#endif +#endif /* 0 */ }