X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Foprofile%2Fop_model_mipsxx.c;h=455d76ad06d83cf1eb3045c3ca6691cb088584c3;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=95d488ca075473be4d4e0a3e0d032a0c413eaf27;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 95d488ca0..455d76ad0 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -3,27 +3,86 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004, 2005 by Ralf Baechle + * Copyright (C) 2004, 05, 06 by Ralf Baechle * Copyright (C) 2005 by MIPS Technologies, Inc. */ #include #include #include +#include #include "op_impl.h" -#define M_PERFCTL_EXL (1UL << 0) -#define M_PERFCTL_KERNEL (1UL << 1) -#define M_PERFCTL_SUPERVISOR (1UL << 2) -#define M_PERFCTL_USER (1UL << 3) -#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) ((event) << 5) -#define M_PERFCTL_WIDE (1UL << 30) -#define M_PERFCTL_MORE (1UL << 31) - -#define M_COUNTER_OVERFLOW (1UL << 31) +#define M_PERFCTL_EXL (1UL << 0) +#define M_PERFCTL_KERNEL (1UL << 1) +#define M_PERFCTL_SUPERVISOR (1UL << 2) +#define M_PERFCTL_USER (1UL << 3) +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) +#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5) +#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) +#define M_PERFCTL_MT_EN(filter) ((filter) << 20) +#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) +#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) +#define M_TC_EN_TC M_PERFCTL_MT_EN(2) +#define M_PERFCTL_TCID(tcid) ((tcid) << 22) +#define M_PERFCTL_WIDE (1UL << 30) +#define M_PERFCTL_MORE (1UL << 31) + +#define M_COUNTER_OVERFLOW (1UL << 31) + +#ifdef CONFIG_MIPS_MT_SMP +#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) +#define vpe_id() smp_processor_id() +#else +#define WHAT 0 +#define vpe_id() smp_processor_id() +#endif -struct op_mips_model op_model_mipsxx; +#define __define_perf_accessors(r, n, np) \ + \ +static inline unsigned int r_c0_ ## r ## n(void) \ +{ \ + unsigned int cpu = vpe_id(); \ + \ + switch (cpu) { \ + case 0: \ + return read_c0_ ## r ## n(); \ + case 1: \ + return read_c0_ ## r ## np(); \ + default: \ + BUG(); \ + } \ + return 0; \ +} \ + \ +static inline void w_c0_ ## r ## n(unsigned int value) \ +{ \ + unsigned int cpu = vpe_id(); \ + \ + switch (cpu) { \ + case 0: \ + write_c0_ ## r ## n(value); \ + return; \ + case 1: \ + write_c0_ ## r ## np(value); \ + return; \ + default: \ + BUG(); \ + } \ + return; \ +} \ + +__define_perf_accessors(perfcntr, 0, 2) +__define_perf_accessors(perfcntr, 1, 3) +__define_perf_accessors(perfcntr, 2, 2) +__define_perf_accessors(perfcntr, 3, 2) + +__define_perf_accessors(perfctrl, 0, 2) +__define_perf_accessors(perfctrl, 1, 3) +__define_perf_accessors(perfctrl, 2, 2) +__define_perf_accessors(perfctrl, 3, 2) + +struct op_mips_model op_model_mipsxx_ops; static struct mipsxx_register_config { unsigned int control[4]; @@ -34,7 +93,7 @@ static struct mipsxx_register_config { static void mipsxx_reg_setup(struct op_counter_config *ctr) { - unsigned int counters = op_model_mipsxx.num_counters; + unsigned int counters = op_model_mipsxx_ops.num_counters; int i; /* Compute the performance counter control word. */ @@ -62,61 +121,61 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr) static void mipsxx_cpu_setup (void *args) { - unsigned int counters = op_model_mipsxx.num_counters; + unsigned int counters = op_model_mipsxx_ops.num_counters; switch (counters) { case 4: - write_c0_perfctrl3(0); - write_c0_perfcntr3(reg.counter[3]); + w_c0_perfctrl3(0); + w_c0_perfcntr3(reg.counter[3]); case 3: - write_c0_perfctrl2(0); - write_c0_perfcntr2(reg.counter[2]); + w_c0_perfctrl2(0); + w_c0_perfcntr2(reg.counter[2]); case 2: - write_c0_perfctrl1(0); - write_c0_perfcntr1(reg.counter[1]); + w_c0_perfctrl1(0); + w_c0_perfcntr1(reg.counter[1]); case 1: - write_c0_perfctrl0(0); - write_c0_perfcntr0(reg.counter[0]); + w_c0_perfctrl0(0); + w_c0_perfcntr0(reg.counter[0]); } } /* Start all counters on current CPU */ static void mipsxx_cpu_start(void *args) { - unsigned int counters = op_model_mipsxx.num_counters; + unsigned int counters = op_model_mipsxx_ops.num_counters; switch (counters) { case 4: - write_c0_perfctrl3(reg.control[3]); + w_c0_perfctrl3(WHAT | reg.control[3]); case 3: - write_c0_perfctrl2(reg.control[2]); + w_c0_perfctrl2(WHAT | reg.control[2]); case 2: - write_c0_perfctrl1(reg.control[1]); + w_c0_perfctrl1(WHAT | reg.control[1]); case 1: - write_c0_perfctrl0(reg.control[0]); + w_c0_perfctrl0(WHAT | reg.control[0]); } } /* Stop all counters on current CPU */ static void mipsxx_cpu_stop(void *args) { - unsigned int counters = op_model_mipsxx.num_counters; + unsigned int counters = op_model_mipsxx_ops.num_counters; switch (counters) { case 4: - write_c0_perfctrl3(0); + w_c0_perfctrl3(0); case 3: - write_c0_perfctrl2(0); + w_c0_perfctrl2(0); case 2: - write_c0_perfctrl1(0); + w_c0_perfctrl1(0); case 1: - write_c0_perfctrl0(0); + w_c0_perfctrl0(0); } } -static int mipsxx_perfcount_handler(struct pt_regs *regs) +static int mipsxx_perfcount_handler(void) { - unsigned int counters = op_model_mipsxx.num_counters; + unsigned int counters = op_model_mipsxx_ops.num_counters; unsigned int control; unsigned int counter; int handled = 0; @@ -124,12 +183,12 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs) switch (counters) { #define HANDLE_COUNTER(n) \ case n + 1: \ - control = read_c0_perfctrl ## n(); \ - counter = read_c0_perfcntr ## n(); \ + control = r_c0_perfctrl ## n(); \ + counter = r_c0_perfcntr ## n(); \ if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ (counter & M_COUNTER_OVERFLOW)) { \ - oprofile_add_sample(regs, n); \ - write_c0_perfcntr ## n(reg.counter[n]); \ + oprofile_add_sample(get_irq_regs(), n); \ + w_c0_perfcntr ## n(reg.counter[n]); \ handled = 1; \ } HANDLE_COUNTER(3) @@ -143,35 +202,57 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs) #define M_CONFIG1_PC (1 << 4) -static inline int n_counters(void) +static inline int __n_counters(void) { if (!(read_c0_config1() & M_CONFIG1_PC)) return 0; - if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) + if (!(r_c0_perfctrl0() & M_PERFCTL_MORE)) return 1; - if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) + if (!(r_c0_perfctrl1() & M_PERFCTL_MORE)) return 2; - if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) + if (!(r_c0_perfctrl2() & M_PERFCTL_MORE)) return 3; return 4; } +static inline int n_counters(void) +{ + int counters; + + switch (current_cpu_data.cputype) { + case CPU_R10000: + counters = 2; + + case CPU_R12000: + case CPU_R14000: + counters = 4; + + default: + counters = __n_counters(); + } + +#ifdef CONFIG_MIPS_MT_SMP + counters >> 1; +#endif + return counters; +} + static inline void reset_counters(int counters) { switch (counters) { case 4: - write_c0_perfctrl3(0); - write_c0_perfcntr3(0); + w_c0_perfctrl3(0); + w_c0_perfcntr3(0); case 3: - write_c0_perfctrl2(0); - write_c0_perfcntr2(0); + w_c0_perfctrl2(0); + w_c0_perfcntr2(0); case 2: - write_c0_perfctrl1(0); - write_c0_perfcntr1(0); + w_c0_perfctrl1(0); + w_c0_perfcntr1(0); case 1: - write_c0_perfctrl0(0); - write_c0_perfcntr0(0); + w_c0_perfctrl0(0); + w_c0_perfcntr0(0); } } @@ -187,33 +268,47 @@ static int __init mipsxx_init(void) reset_counters(counters); - op_model_mipsxx.num_counters = counters; + op_model_mipsxx_ops.num_counters = counters; switch (current_cpu_data.cputype) { case CPU_20KC: - op_model_mipsxx.cpu_type = "mips/20K"; + op_model_mipsxx_ops.cpu_type = "mips/20K"; break; case CPU_24K: - op_model_mipsxx.cpu_type = "mips/24K"; + op_model_mipsxx_ops.cpu_type = "mips/24K"; break; case CPU_25KF: - op_model_mipsxx.cpu_type = "mips/25K"; + op_model_mipsxx_ops.cpu_type = "mips/25K"; break; -#ifndef CONFIG_SMP case CPU_34K: - op_model_mipsxx.cpu_type = "mips/34K"; + op_model_mipsxx_ops.cpu_type = "mips/34K"; + break; + + case CPU_74K: + op_model_mipsxx_ops.cpu_type = "mips/74K"; break; -#endif case CPU_5KC: - op_model_mipsxx.cpu_type = "mips/5K"; + op_model_mipsxx_ops.cpu_type = "mips/5K"; + break; + + case CPU_R10000: + if ((current_cpu_data.processor_id & 0xff) == 0x20) + op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x"; + else + op_model_mipsxx_ops.cpu_type = "mips/r10000"; + break; + + case CPU_R12000: + case CPU_R14000: + op_model_mipsxx_ops.cpu_type = "mips/r12000"; break; case CPU_SB1: case CPU_SB1A: - op_model_mipsxx.cpu_type = "mips/sb1"; + op_model_mipsxx_ops.cpu_type = "mips/sb1"; break; default: @@ -229,12 +324,12 @@ static int __init mipsxx_init(void) static void mipsxx_exit(void) { - reset_counters(op_model_mipsxx.num_counters); + reset_counters(op_model_mipsxx_ops.num_counters); perf_irq = null_perf_irq; } -struct op_mips_model op_model_mipsxx = { +struct op_mips_model op_model_mipsxx_ops = { .reg_setup = mipsxx_reg_setup, .cpu_setup = mipsxx_cpu_setup, .init = mipsxx_init,