X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fpci%2Fpci-yosemite.c;h=dac9ed4b0ccf690df67474b92b4774a8e0c8f2e7;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=c1151f43c9af7e8e0cbdea147adbef592918d79c;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git

diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
index c1151f43c..dac9ed4b0 100644
--- a/arch/mips/pci/pci-yosemite.c
+++ b/arch/mips/pci/pci-yosemite.c
@@ -3,15 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004 by Ralf Baechle
- *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/pci.h>
-#include <asm/gt64240.h>
-#include <asm/pci_channel.h>
+#include <asm/titan_dep.h>
 
 extern struct pci_ops titan_pci_ops;
 
@@ -19,19 +17,44 @@ static struct resource py_mem_resource = {
 	"Titan PCI MEM", 0xe0000000UL, 0xe3ffffffUL, IORESOURCE_MEM
 };
 
+/*
+ * PMON really reserves 16MB of I/O port space but that's stupid, nothing
+ * needs that much since allocations are limited to 256 bytes per device
+ * anyway.  So we just claim 64kB here.
+ */
+#define TITAN_IO_SIZE	0x0000ffffUL
+#define TITAN_IO_BASE	0xe8000000UL
+
 static struct resource py_io_resource = {
-	"Titan IO MEM", 0x00000000UL, 0x00ffffffUL, IORESOURCE_IO,
+	"Titan IO MEM", 0x00001000UL, TITAN_IO_SIZE - 1, IORESOURCE_IO,
 };
 
 static struct pci_controller py_controller = {
 	.pci_ops	= &titan_pci_ops,
 	.mem_resource	= &py_mem_resource,
-	.mem_offset	= 0x10000000UL,
+	.mem_offset	= 0x00000000UL,
 	.io_resource	= &py_io_resource,
 	.io_offset	= 0x00000000UL
 };
 
+static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
+
 static int __init pmc_yosemite_setup(void)
 {
+	unsigned long io_v_base;
+
+	io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
+	if (!io_v_base)
+		panic(ioremap_failed);
+
+	set_io_port_base(io_v_base);
+	TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
+
+	ioport_resource.end = TITAN_IO_SIZE - 1;
+
 	register_pci_controller(&py_controller);
+
+	return 0;
 }
+
+arch_initcall(pmc_yosemite_setup);