X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fmips%2Fsibyte%2Fsb1250%2Firq.c;h=0f6e54db4888869c35d639fdc9963a602e62ad8c;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=ddbe64b2d371985da32f8d20670a8eb4adabb4c5;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index ddbe64b2d..0f6e54db4 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -53,7 +53,7 @@ static void disable_sb1250_irq(unsigned int irq); static unsigned int startup_sb1250_irq(unsigned int irq); static void ack_sb1250_irq(unsigned int irq); #ifdef CONFIG_SMP -static void sb1250_set_affinity(unsigned int irq, unsigned long mask); +static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); #endif #ifdef CONFIG_SIBYTE_HAS_LDT @@ -61,19 +61,8 @@ extern unsigned long ldt_eoi_space; #endif #ifdef CONFIG_KGDB -#include -extern void breakpoint(void); static int kgdb_irq; -/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */ -static int kgdb_flag = 1; -static int __init nokgdb(char *str) -{ - kgdb_flag = 0; - return 1; -} -__setup("nokgdb", nokgdb); - /* Default to UART1 */ int kgdb_port = 1; #ifdef CONFIG_SIBYTE_SB1250_DUART @@ -82,24 +71,22 @@ extern char sb1250_duart_present[]; #endif static struct hw_interrupt_type sb1250_irq_type = { - "SB1250-IMR", - startup_sb1250_irq, - shutdown_sb1250_irq, - enable_sb1250_irq, - disable_sb1250_irq, - ack_sb1250_irq, - end_sb1250_irq, + .typename = "SB1250-IMR", + .startup = startup_sb1250_irq, + .shutdown = shutdown_sb1250_irq, + .enable = enable_sb1250_irq, + .disable = disable_sb1250_irq, + .ack = ack_sb1250_irq, + .end = end_sb1250_irq, #ifdef CONFIG_SMP - sb1250_set_affinity -#else - NULL + .set_affinity = sb1250_set_affinity #endif }; /* Store the CPU id (not the logical number) */ int sb1250_irq_owner[SB1250_NR_IRQS]; -spinlock_t sb1250_imr_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(sb1250_imr_lock); void sb1250_mask_irq(int cpu, int irq) { @@ -107,9 +94,11 @@ void sb1250_mask_irq(int cpu, int irq) u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints |= (((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } @@ -119,30 +108,25 @@ void sb1250_unmask_irq(int cpu, int irq) u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } #ifdef CONFIG_SMP -static void sb1250_set_affinity(unsigned int irq, unsigned long mask) +static void sb1250_set_affinity(unsigned int irq, cpumask_t mask) { int i = 0, old_cpu, cpu, int_on; u64 cur_ints; irq_desc_t *desc = irq_desc + irq; unsigned long flags; - while (mask) { - if (mask & 1) { - mask >>= 1; - break; - } - mask >>= 1; - i++; - } + i = first_cpu(mask); - if (mask) { + if (cpus_weight(mask) > 1) { printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); return; } @@ -156,29 +140,29 @@ static void sb1250_set_affinity(unsigned int irq, unsigned long mask) /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); int_on = !(cur_ints & (((u64) 1) << irq)); if (int_on) { /* If it was on, mask it */ cur_ints |= (((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); } sb1250_irq_owner[irq] = cpu; if (int_on) { /* unmask for the new CPU */ - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); } spin_unlock(&sb1250_imr_lock); spin_unlock_irqrestore(&desc->lock, flags); } #endif - -/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */ -extern void sb1250_irq_handler(void); - /*****************************************************************************/ static unsigned int startup_sb1250_irq(unsigned int irq) @@ -227,8 +211,9 @@ static void ack_sb1250_irq(unsigned int irq) * Clear for all CPUs so an affinity switch * doesn't find an old status */ - __raw_writeq(pending, - IOADDR(A_IMR_REGISTER(cpu, R_IMR_LDT_INTERRUPT_CLR))); + __raw_writeq(pending, + IOADDR(A_IMR_REGISTER(cpu, + R_IMR_LDT_INTERRUPT_CLR))); } /* @@ -307,10 +292,10 @@ int sb1250_steal_irq(int irq) } /* - * init_IRQ is called early in the boot sequence from init/main.c. It - * is responsible for setting up the interrupt mapper and installing the - * handler that will be responsible for dispatching interrupts to the - * "right" place. + * arch_init_irq is called early in the boot sequence from init/main.c via + * init_IRQ. It is responsible for setting up the interrupt mapper and + * installing the handler that will be responsible for dispatching interrupts + * to the "right" place. */ /* * For now, map all interrupts to IP[2]. We could save @@ -332,7 +317,7 @@ int sb1250_steal_irq(int irq) #define IMR_IP5_VAL K_INT_MAP_I3 #define IMR_IP6_VAL K_INT_MAP_I4 -void __init init_IRQ(void) +void __init arch_init_irq(void) { unsigned int i; @@ -348,7 +333,7 @@ void __init init_IRQ(void) (i << 3))); __raw_writeq(IMR_IP2_VAL, IOADDR(A_IMR_REGISTER(1, - R_IMR_INTERRUPT_MAP_BASE) + + R_IMR_INTERRUPT_MAP_BASE) + (i << 3))); } @@ -359,15 +344,17 @@ void __init init_IRQ(void) * inter-cpu messages */ /* Was I1 */ - __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); - __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); + __raw_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); + __raw_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); /* Clear the mailboxes. The firmware may leave them dirty */ - __raw_writeq(0xffffffffffffffff, + __raw_writeq(0xffffffffffffffffULL, IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); - __raw_writeq(0xffffffffffffffff, + __raw_writeq(0xffffffffffffffffULL, IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); /* Mask everything except the mailbox registers for both cpus */ @@ -379,7 +366,7 @@ void __init init_IRQ(void) /* * Note that the timer interrupts are also mapped, but this is - * done in sb1250_time_init(). Also, the profiling driver + * done in sb1250_time_init(). Also, the profiling driver * does its own management of IP7. */ @@ -388,27 +375,24 @@ void __init init_IRQ(void) #endif /* Enable necessary IPs, disable the rest */ change_c0_status(ST0_IM, imask); - set_except_vector(0, sb1250_irq_handler); #ifdef CONFIG_KGDB if (kgdb_flag) { kgdb_irq = K_INT_UART_0 + kgdb_port; -#ifdef CONFIG_SIBYTE_SB1250_DUART +#ifdef CONFIG_SIBYTE_SB1250_DUART sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ - __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); + __raw_writeq(M_DUART_IMR_BRK, + IOADDR(A_DUART_IMRREG(kgdb_port))); sb1250_steal_irq(kgdb_irq); __raw_writeq(IMR_IP6_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (kgdb_irq<<3))); + IOADDR(A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (kgdb_irq << 3))); sb1250_unmask_irq(0, kgdb_irq); - - prom_printf("Waiting for GDB on UART port %d\n", kgdb_port); - set_debug_traps(); - breakpoint(); } #endif } @@ -420,7 +404,7 @@ void __init init_IRQ(void) #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) -void sb1250_kgdb_interrupt(struct pt_regs *regs) +static void sb1250_kgdb_interrupt(struct pt_regs *regs) { /* * Clear break-change status (allow some time for the remote @@ -435,3 +419,74 @@ void sb1250_kgdb_interrupt(struct pt_regs *regs) } #endif /* CONFIG_KGDB */ + +static inline int dclz(unsigned long long x) +{ + int lz; + + __asm__ ( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (lz) + : "r" (x)); + + return lz; +} + +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending; + +#ifdef CONFIG_SIBYTE_SB1250_PROF + /* Set compare to count to silence count/compare timer interrupts */ + write_c0_count(read_c0_count()); +#endif + + /* + * What a pain. We have to be really careful saving the upper 32 bits + * of any * register across function calls if we don't want them + * trashed--since were running in -o32, the calling routing never saves + * the full 64 bits of a register across a function call. Being the + * interrupt handler, we're guaranteed that interrupts are disabled + * during this code so we don't have to worry about random interrupts + * blasting the high 32 bits. + */ + + pending = read_c0_cause(); + +#ifdef CONFIG_SIBYTE_SB1250_PROF + if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */ + sbprof_cpu_intr(exception_epc(regs)); + } +#endif + + if (pending & CAUSEF_IP4) + sb1250_timer_interrupt(regs); + +#ifdef CONFIG_SMP + if (pending & CAUSEF_IP3) + sb1250_mailbox_interrupt(regs); +#endif + +#ifdef CONFIG_KGDB + if (pending & CAUSEF_IP6) /* KGDB (uart 1) */ + sb1250_kgdb_interrupt(regs); +#endif + + if (pending & CAUSEF_IP2) { + unsigned long long mask; + + /* + * Default...we've hit an IP[2] interrupt, which means we've + * got to check the 1250 interrupt registers to figure out what + * to do. Need to detect which CPU we're on, now that + ~ smp_affinity is supported. + */ + mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), + R_IMR_INTERRUPT_STATUS_BASE))); + if (mask) + do_IRQ(63 - dclz(mask), regs); + } +}