X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fparisc%2Fkernel%2Fcache.c;h=c057ad7605bab4e8e3d4d1ac1e987bced680f780;hb=9464c7cf61b9433057924c36e6e02f303a00e768;hp=bc7c4a4e26a1e24f53b62b735bf820baac104635;hpb=41689045f6a3cbe0550e1d34e9cc20d2e8c432ba;p=linux-2.6.git

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index bc7c4a4e2..c057ad760 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -97,17 +97,15 @@ update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 void
 show_cache_info(struct seq_file *m)
 {
-	char buf[32];
-
 	seq_printf(m, "I-cache\t\t: %ld KB\n", 
 		cache_info.ic_size/1024 );
-	if (cache_info.dc_loop == 1)
-		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
-	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
+	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n", 
 		cache_info.dc_size/1024,
 		(cache_info.dc_conf.cc_wt ? "WT":"WB"),
 		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
-		((cache_info.dc_loop == 1) ? "direct mapped" : buf));
+		(cache_info.dc_conf.cc_assoc)
+	);
+
 	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 		cache_info.it_size,
 		cache_info.dt_size,
@@ -160,11 +158,11 @@ parisc_cache_init(void)
 		cache_info.dc_conf.cc_block,
 		cache_info.dc_conf.cc_line,
 		cache_info.dc_conf.cc_shift);
-	printk("	wt %d sh %d cst %d hv %d\n",
+	printk("	wt %d sh %d cst %d assoc %d\n",
 		cache_info.dc_conf.cc_wt,
 		cache_info.dc_conf.cc_sh,
 		cache_info.dc_conf.cc_cst,
-		cache_info.dc_conf.cc_hv);
+		cache_info.dc_conf.cc_assoc);
 
 	printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 		cache_info.ic_base,
@@ -178,11 +176,11 @@ parisc_cache_init(void)
 		cache_info.ic_conf.cc_block,
 		cache_info.ic_conf.cc_line,
 		cache_info.ic_conf.cc_shift);
-	printk("	wt %d sh %d cst %d hv %d\n",
+	printk("	wt %d sh %d cst %d assoc %d\n",
 		cache_info.ic_conf.cc_wt,
 		cache_info.ic_conf.cc_sh,
 		cache_info.ic_conf.cc_cst,
-		cache_info.ic_conf.cc_hv);
+		cache_info.ic_conf.cc_assoc);
 
 	printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 		cache_info.dt_conf.tc_sh,
@@ -236,8 +234,7 @@ parisc_cache_init(void)
 
 void disable_sr_hashing(void)
 {
-	int srhash_type, retval;
-	unsigned long space_bits;
+	int srhash_type;
 
 	switch (boot_cpu_data.cpu_type) {
 	case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
@@ -263,13 +260,6 @@ void disable_sr_hashing(void)
 	}
 
 	disable_sr_hashing_asm(srhash_type);
-
-	retval = pdc_spaceid_bits(&space_bits);
-	/* If this procedure isn't implemented, don't panic. */
-	if (retval < 0 && retval != PDC_BAD_OPTION)
-		panic("pdc_spaceid_bits call failed.\n");
-	if (space_bits != 0)
-		panic("SpaceID hashing is still on!\n");
 }
 
 void flush_dcache_page(struct page *page)