X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fboot%2Fsimple%2Fembed_config.c;h=840bff2a45fb8bcaf2c06eb252bb0dbe769ae303;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=be0b6ca2477f237fcdb8d44ff975de0c744b3767;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git diff --git a/arch/ppc/boot/simple/embed_config.c b/arch/ppc/boot/simple/embed_config.c index be0b6ca24..840bff2a4 100644 --- a/arch/ppc/boot/simple/embed_config.c +++ b/arch/ppc/boot/simple/embed_config.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #ifdef CONFIG_8xx @@ -21,6 +20,9 @@ #ifdef CONFIG_40x #include #endif +#ifdef CONFIG_XILINX_VIRTEX +#include +#endif extern unsigned long timebase_period_ns; /* For those boards that don't provide one. @@ -506,7 +508,7 @@ embed_config(bd_t **bdp) memcpy(bd->bi_enetaddr, cp, 6); /* can busfreq be calculated? */ - pvr = mfspr(PVR); + pvr = mfspr(SPRN_PVR); if ((pvr & 0xffff0000) == 0x80820000) { bd->bi_busfreq = 100000000; clk_8280(bd); @@ -742,32 +744,32 @@ embed_config(bd_t **bdp) } #endif /* WILLOW */ -#ifdef CONFIG_XILINX_ML300 +#if defined(CONFIG_XILINX_ML300) || defined(CONFIG_XILINX_ML403) void embed_config(bd_t ** bdp) { static const unsigned long line_size = 32; static const unsigned long congruence_classes = 256; unsigned long addr; - u_char *cp; - int i; + unsigned long dccr; bd_t *bd; /* - * At one point, we were getting machine checks. Linux was not - * invalidating the data cache before it was enabled. The - * following code was added to do that. Soon after we had done - * that, we found the real reasons for the machine checks. I've - * run the kernel a few times with the following code - * temporarily removed without any apparent problems. However, - * I objdump'ed the kernel and boot code and found out that - * there were no other dccci's anywhere, so I put the code back - * in and have been reluctant to remove it. It seems safer to - * just leave it here. + * Invalidate the data cache if the data cache is turned off. + * - The 405 core does not invalidate the data cache on power-up + * or reset but does turn off the data cache. We cannot assume + * that the cache contents are valid. + * - If the data cache is turned on this must have been done by + * a bootloader and we assume that the cache contents are + * valid. */ - for (addr = 0; - addr < (congruence_classes * line_size); addr += line_size) { - __asm__("dccci 0,%0": :"b"(addr)); + __asm__("mfdccr %0": "=r" (dccr)); + if (dccr == 0) { + for (addr = 0; + addr < (congruence_classes * line_size); + addr += line_size) { + __asm__("dccci 0,%0": :"b"(addr)); + } } bd = &bdinfo; @@ -775,34 +777,21 @@ embed_config(bd_t ** bdp) bd->bi_memsize = XPAR_DDR_0_SIZE; bd->bi_intfreq = XPAR_CORE_CLOCK_FREQ_HZ; bd->bi_busfreq = XPAR_PLB_CLOCK_FREQ_HZ; + bd->bi_pci_busfreq = XPAR_PCI_0_CLOCK_FREQ_HZ; + timebase_period_ns = 1000000000 / bd->bi_tbfreq; + /* see bi_tbfreq definition in arch/ppc/platforms/4xx/xilinx_ml300.h */ } -#endif /* CONFIG_XILINX_ML300 */ +#endif /* CONFIG_XILINX_ML300 || CONFIG_XILINX_ML403 */ #ifdef CONFIG_IBM_OPENBIOS /* This could possibly work for all treeboot roms. */ -#if defined(CONFIG_ASH) || defined(CONFIG_BEECH) || defined(CONFIG_BUBINGA) +#if defined(CONFIG_BUBINGA) #define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */ #else #define BOARD_INFO_VECTOR 0xFFFE0B50 #endif -#ifdef CONFIG_BEECH -static void -get_board_info(bd_t **bdp) -{ - typedef void (*PFV)(bd_t *bd); - ((PFV)(*(unsigned long *)BOARD_INFO_VECTOR))(*bdp); - return; -} - -void -embed_config(bd_t **bdp) -{ - *bdp = &bdinfo; - get_board_info(bdp); -} -#else /* !CONFIG_BEECH */ void embed_config(bd_t **bdp) { @@ -857,7 +846,6 @@ embed_config(bd_t **bdp) #endif timebase_period_ns = 1000000000 / bd->bi_tbfreq; } -#endif /* CONFIG_BEECH */ #endif /* CONFIG_IBM_OPENBIOS */ #ifdef CONFIG_EP405 @@ -940,39 +928,3 @@ embed_config(bd_t **bdp) #endif } #endif - -#ifdef CONFIG_RAINIER -/* Rainier uses vxworks bootrom */ -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - bd = &bdinfo; - *bdp = bd; - - for(i=0;i<8192;i+=32) { - __asm__("dccci 0,%0" :: "r" (i)); - } - __asm__("iccci 0,0"); - __asm__("sync;isync"); - - /* init ram for parity */ - memset(0, 0,0x400000); /* Lo memory */ - - - bd->bi_memsize = (32 * 1024 * 1024) ; - bd->bi_intfreq = 133000000; //the internal clock is 133 MHz - bd->bi_busfreq = 100000000; - bd->bi_pci_busfreq= 33000000; - - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } - -} -#endif -