X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fboot%2Fsimple%2Fmisc-ev64260.S;h=2dc3e6c5032afc16affddb0a54c6be55af22dd98;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=7ce68158deb1570f0e72b0342b8b68befeb30d87;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git diff --git a/arch/ppc/boot/simple/misc-ev64260.S b/arch/ppc/boot/simple/misc-ev64260.S index 7ce68158d..2dc3e6c50 100644 --- a/arch/ppc/boot/simple/misc-ev64260.S +++ b/arch/ppc/boot/simple/misc-ev64260.S @@ -6,55 +6,63 @@ * * Author: Mark Greer * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program + * 2001 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. */ #include +#include #include -#include - +#include #include - .globl ev64260_init -ev64260_init: - li r20,0 + .globl mv64x60_board_init +mv64x60_board_init: + /* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */ + mfspr r25,PVR + srwi r25,r25,16 + cmplwi r25,(PVR_7450 >> 16) + bne 1f + mfspr r25,HID0 + oris r25,r25,(HID0_TBEN >> 16) + mtspr HID0,r25 +1: +#if (CONFIG_MV64X60_NEW_BASE != CONFIG_MV64X60_BASE) li r23,20 - /* Relocate galileo's regs */ - addis r25,0,GT64260_INTERNAL_SPACE_DEFAULT_ADDR@h - ori r25,r25,GT64260_INTERNAL_SPACE_DECODE - lwbrx r26,0,(r25) - lis r24,0xffff - and r26,r26,r24 - addis r24,0,EV64260_BRIDGE_REG_BASE@h - srw r24,r24,r23 - or r26,r26,r24 - stwbrx r26,0,(r25) - sync - - /* Wait for write to take effect */ - addis r25,0,EV64260_BRIDGE_REG_BASE@h - ori r25,r25,GT64260_INTERNAL_SPACE_DECODE -1: lwbrx r24,0,(r25) - cmpw r24,r26 - bne 1b - - /* Change CS2 (UARTS on device module) window */ - addis r25,0,EV64260_BRIDGE_REG_BASE@h - ori r25,r25,GT64260_CPU_CS_DECODE_2_BOT + /* + * Change the CS2 window for the UART so that the bootloader + * can do I/O thru the UARTs. + */ + addis r25,0,CONFIG_MV64X60_NEW_BASE@h + ori r25,r25,MV64x60_CPU2DEV_2_BASE addis r26,0,EV64260_UART_BASE@h srw r26,r26,r23 - stwbrx r26,0,(r25) + stwbrx r26,0,(r25) sync - addis r25,0,EV64260_BRIDGE_REG_BASE@h - ori r25,r25,GT64260_CPU_CS_DECODE_2_TOP + addis r25,0,CONFIG_MV64X60_NEW_BASE@h + ori r25,r25,MV64x60_CPU2DEV_2_SIZE addis r26,0,EV64260_UART_END@h srw r26,r26,r23 - stwbrx r26,0,(r25) + stwbrx r26,0,(r25) sync +#endif + blr + +#if defined(CONFIG_SERIAL_MPSC_CONSOLE) +.data + .globl mv64x60_console_baud +mv64x60_console_baud: +.long EV64260_DEFAULT_BAUD + + .globl mv64x60_mpsc_clk_src +mv64x60_mpsc_clk_src: +.long EV64260_MPSC_CLK_SRC - blr + .globl mv64x60_mpsc_clk_freq +mv64x60_mpsc_clk_freq: +.long EV64260_MPSC_CLK_FREQ +#endif