X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fkernel%2Fhead_44x.S;h=0d8b88219d3880ac2e8d966a77850cfe99e8853a;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=1dc13796973b6a37ebb0d63a8e72d57a1072d688;hpb=6a77f38946aaee1cd85eeec6cf4229b204c15071;p=linux-2.6.git diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S index 1dc137969..0d8b88219 100644 --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -1,6 +1,4 @@ /* - * arch/ppc/kernel/head_44x.S - * * Kernel execution entry point code. * * Copyright (c) 1995-1996 Gary Thomas @@ -40,7 +38,7 @@ #include #include #include -#include +#include #include "head_booke.h" @@ -162,10 +160,10 @@ skpinv: addi r4,r4,1 /* Increment */ /* Force context change */ mfmsr r0 - mtspr SRR1, r0 + mtspr SPRN_SRR1, r0 lis r0,3f@h ori r0,r0,3f@l - mtspr SRR0,r0 + mtspr SPRN_SRR0,r0 sync rfi @@ -179,24 +177,26 @@ skpinv: addi r4,r4,1 /* Increment */ 4: #ifdef CONFIG_SERIAL_TEXT_DEBUG /* - * Add temporary UART mapping for early debug. This - * mapping must be identical to that used by the early - * bootloader code since the same asm/serial.h parameters - * are used for polled operation. + * Add temporary UART mapping for early debug. + * We can map UART registers wherever we want as long as they don't + * interfere with other system mappings (e.g. with pinned entries). + * For an example of how we handle this - see ocotea.h. --ebs */ /* pageid fields */ lis r3,UART0_IO_BASE@h - ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M + ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K /* xlat fields */ lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ - ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ +#ifdef UART0_PHYS_ERPN + ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */ +#endif /* attrib fields */ li r5,0 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G) - li r0,1 /* TLB slot 1 */ + li r0,0 /* TLB slot 0 */ tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ @@ -228,6 +228,16 @@ skpinv: addi r4,r4,1 /* Increment */ lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ mtspr SPRN_IVPR,r4 +#ifdef CONFIG_440EP + /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */ + mfspr r2,SPRN_CCR0 + lis r3,0xffef + ori r3,r3,0xffff + and r2,r2,r3 + mtspr SPRN_CCR0,r2 + isync +#endif + /* * This is where the main kernel code starts. */ @@ -238,7 +248,7 @@ skpinv: addi r4,r4,1 /* Increment */ /* ptr to current thread */ addi r4,r2,THREAD /* init task's THREAD */ - mtspr SPRG3,r4 + mtspr SPRN_SPRG3,r4 /* stack */ lis r1,init_thread_union@h @@ -274,8 +284,8 @@ skpinv: addi r4,r4,1 /* Increment */ ori r4,r4,start_kernel@l lis r3,MSR_KERNEL@h ori r3,r3,MSR_KERNEL@l - mtspr SRR0,r4 - mtspr SRR1,r3 + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 rfi /* change context and jump to start_kernel */ /* @@ -297,23 +307,23 @@ skpinv: addi r4,r4,1 /* Increment */ interrupt_base: /* Critical Input Interrupt */ - CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException) + CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) /* Machine Check Interrupt */ #ifdef CONFIG_440A - MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException) + MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) #else - CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException) + CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) #endif /* Data Storage Interrupt */ START_EXCEPTION(DataStorage) - mtspr SPRG0, r10 /* Save some working registers */ - mtspr SPRG1, r11 - mtspr SPRG4W, r12 - mtspr SPRG5W, r13 + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 mfcr r11 - mtspr SPRG7W, r11 + mtspr SPRN_SPRG7W, r11 /* * Check if it was a store fault, if not then bail @@ -330,8 +340,9 @@ interrupt_base: /* If we are faulting a kernel address, we have to use the * kernel page tables. */ - andis. r11, r10, 0x8000 - beq 3f + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f lis r11, swapper_pg_dir@h ori r11, r11, swapper_pg_dir@l @@ -342,7 +353,7 @@ interrupt_base: /* Get the PGD for the current thread */ 3: - mfspr r11,SPRG3 + mfspr r11,SPRN_SPRG3 lwz r11,PGDIR(r11) /* Load PID into MMUCR TID */ @@ -390,13 +401,13 @@ interrupt_base: /* Done...restore registers and get out of here. */ - mfspr r11, SPRG7R + mfspr r11, SPRN_SPRG7R mtcr r11 - mfspr r13, SPRG5R - mfspr r12, SPRG4R + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R - mfspr r11, SPRG1 - mfspr r10, SPRG0 + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 rfi /* Force context change */ 2: @@ -404,13 +415,13 @@ interrupt_base: * The bailout. Restore registers to pre-exception conditions * and call the heavyweights to help us out. */ - mfspr r11, SPRG7R + mfspr r11, SPRN_SPRG7R mtcr r11 - mfspr r13, SPRG5R - mfspr r12, SPRG4R + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R - mfspr r11, SPRG1 - mfspr r10, SPRG0 + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 b data_access /* Instruction Storage Interrupt */ @@ -426,7 +437,11 @@ interrupt_base: PROGRAM_EXCEPTION /* Floating Point Unavailable Interrupt */ - EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE) +#ifdef CONFIG_PPC_FPU + FP_UNAVAILABLE_EXCEPTION +#else + EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) +#endif /* System Call Interrupt */ START_EXCEPTION(SystemCall) @@ -434,34 +449,39 @@ interrupt_base: EXC_XFER_EE_LITE(0x0c00, DoSyscall) /* Auxillary Processor Unavailable Interrupt */ - EXCEPTION(0x2020, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) /* Decrementer Interrupt */ DECREMENTER_EXCEPTION /* Fixed Internal Timer Interrupt */ /* TODO: Add FIT support */ - EXCEPTION(0x1010, FixedIntervalTimer, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) /* Watchdog Timer Interrupt */ /* TODO: Add watchdog support */ - CRITICAL_EXCEPTION(0x1020, WatchdogTimer, UnknownException) +#ifdef CONFIG_BOOKE_WDT + CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException) +#else + CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception) +#endif /* Data TLB Error Interrupt */ START_EXCEPTION(DataTLBError) - mtspr SPRG0, r10 /* Save some working registers */ - mtspr SPRG1, r11 - mtspr SPRG4W, r12 - mtspr SPRG5W, r13 + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 mfcr r11 - mtspr SPRG7W, r11 + mtspr SPRN_SPRG7W, r11 mfspr r10, SPRN_DEAR /* Get faulting address */ /* If we are faulting a kernel address, we have to use the * kernel page tables. */ - andis. r11, r10, 0x8000 - beq 3f + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f lis r11, swapper_pg_dir@h ori r11, r11, swapper_pg_dir@l @@ -472,7 +492,7 @@ interrupt_base: /* Get the PGD for the current thread */ 3: - mfspr r11,SPRG3 + mfspr r11,SPRN_SPRG3 lwz r11,PGDIR(r11) /* Load PID into MMUCR TID */ @@ -503,12 +523,12 @@ interrupt_base: /* The bailout. Restore registers to pre-exception conditions * and call the heavyweights to help us out. */ - mfspr r11, SPRG7R + mfspr r11, SPRN_SPRG7R mtcr r11 - mfspr r13, SPRG5R - mfspr r12, SPRG4R - mfspr r11, SPRG1 - mfspr r10, SPRG0 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 b data_access /* Instruction TLB Error Interrupt */ @@ -518,19 +538,20 @@ interrupt_base: * to a different point. */ START_EXCEPTION(InstructionTLBError) - mtspr SPRG0, r10 /* Save some working registers */ - mtspr SPRG1, r11 - mtspr SPRG4W, r12 - mtspr SPRG5W, r13 + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 mfcr r11 - mtspr SPRG7W, r11 - mfspr r10, SRR0 /* Get faulting address */ + mtspr SPRN_SPRG7W, r11 + mfspr r10, SPRN_SRR0 /* Get faulting address */ /* If we are faulting a kernel address, we have to use the * kernel page tables. */ - andis. r11, r10, 0x8000 - beq 3f + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f lis r11, swapper_pg_dir@h ori r11, r11, swapper_pg_dir@l @@ -541,7 +562,7 @@ interrupt_base: /* Get the PGD for the current thread */ 3: - mfspr r11,SPRG3 + mfspr r11,SPRN_SPRG3 lwz r11,PGDIR(r11) /* Load PID into MMUCR TID */ @@ -572,12 +593,12 @@ interrupt_base: /* The bailout. Restore registers to pre-exception conditions * and call the heavyweights to help us out. */ - mfspr r11, SPRG7R + mfspr r11, SPRN_SPRG7R mtcr r11 - mfspr r13, SPRG5R - mfspr r12, SPRG4R - mfspr r11, SPRG1 - mfspr r10, SPRG0 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 b InstructionStorage /* Debug Interrupt */ @@ -661,12 +682,12 @@ finish_tlb_load: /* Done...restore registers and get out of here. */ - mfspr r11, SPRG7R + mfspr r11, SPRN_SPRG7R mtcr r11 - mfspr r13, SPRG5R - mfspr r12, SPRG4R - mfspr r11, SPRG1 - mfspr r10, SPRG0 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 rfi /* Force context change */ /* @@ -686,8 +707,10 @@ _GLOBAL(giveup_altivec) * * The 44x core does not have an FPU. */ +#ifndef CONFIG_PPC_FPU _GLOBAL(giveup_fpu) blr +#endif /* * extern void abort(void) @@ -718,94 +741,35 @@ _GLOBAL(set_context) * goes at the beginning of the data segment, which is page-aligned. */ .data -_GLOBAL(sdata) -_GLOBAL(empty_zero_page) + .align 12 + .globl sdata +sdata: + .globl empty_zero_page +empty_zero_page: .space 4096 /* * To support >32-bit physical addresses, we use an 8KB pgdir. */ -_GLOBAL(swapper_pg_dir) + .globl swapper_pg_dir +swapper_pg_dir: .space 8192 +/* Reserved 4k for the critical exception stack & 4k for the machine + * check stack per CPU for kernel mode exceptions */ .section .bss -/* Stack for handling critical exceptions from kernel mode */ -critical_stack_bottom: - .space 4096 -critical_stack_top: - .previous - -/* Stack for handling machine check exceptions from kernel mode */ -mcheck_stack_bottom: - .space 4096 -mcheck_stack_top: - .previous - -/* - * This area is used for temporarily saving registers during the - * critical and machine check exception prologs. It must always - * follow the page aligned allocations, so it starts on a page - * boundary, ensuring that all crit_save areas are in a single - * page. - */ - -/* crit_save */ -_GLOBAL(crit_save) - .space 4 -_GLOBAL(crit_r10) - .space 4 -_GLOBAL(crit_r11) - .space 4 -_GLOBAL(crit_sprg0) - .space 4 -_GLOBAL(crit_sprg1) - .space 4 -_GLOBAL(crit_sprg4) - .space 4 -_GLOBAL(crit_sprg5) - .space 4 -_GLOBAL(crit_sprg7) - .space 4 -_GLOBAL(crit_pid) - .space 4 -_GLOBAL(crit_srr0) - .space 4 -_GLOBAL(crit_srr1) - .space 4 - -/* mcheck_save */ -_GLOBAL(mcheck_save) - .space 4 -_GLOBAL(mcheck_r10) - .space 4 -_GLOBAL(mcheck_r11) - .space 4 -_GLOBAL(mcheck_sprg0) - .space 4 -_GLOBAL(mcheck_sprg1) - .space 4 -_GLOBAL(mcheck_sprg4) - .space 4 -_GLOBAL(mcheck_sprg5) - .space 4 -_GLOBAL(mcheck_sprg7) - .space 4 -_GLOBAL(mcheck_pid) - .space 4 -_GLOBAL(mcheck_srr0) - .space 4 -_GLOBAL(mcheck_srr1) - .space 4 -_GLOBAL(mcheck_csrr0) - .space 4 -_GLOBAL(mcheck_csrr1) - .space 4 + .align 12 +exception_stack_bottom: + .space BOOKE_EXCEPTION_STACK_SIZE + .globl exception_stack_top +exception_stack_top: /* * This space gets a copy of optional info passed to us by the bootstrap * which is used to pass parameters into the kernel like root=/dev/sda1, etc. */ -_GLOBAL(cmd_line) + .globl cmd_line +cmd_line: .space 512 /* @@ -814,5 +778,3 @@ _GLOBAL(cmd_line) */ abatron_pteptrs: .space 8 - -