X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2F4xx%2Febony.c;h=f0f9cc8480ca94d1e788e321112a700dcf94eaa0;hb=refs%2Fheads%2Fvserver;hp=118d8520e38b460a75aa29a0c6de6cabf14b8122;hpb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;p=linux-2.6.git diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index 118d8520e..f0f9cc848 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -1,13 +1,11 @@ /* - * arch/ppc/platforms/ebony.c - * * Ebony board specific routines * - * Matt Porter - * Copyright 2002 MontaVista Software Inc. + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. * * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies + * Copyright (c) 2003-2005 Zultys Technologies * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -15,7 +13,6 @@ * option) any later version. */ -#include #include #include #include @@ -30,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -49,79 +45,35 @@ #include #include #include +#include +#include + +#include +#include + +extern bd_t __res; + +static struct ibm44x_clocks clocks __initdata; /* - * Ebony IRQ triggering/polarity settings + * Ebony external IRQ triggering/polarity settings */ -static u_char ebony_IRQ_initsenses[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: UART 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: UART 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: IIC 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI Inb Mess */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: PCI Cmd Wrt */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: PCI PM */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 7: PCI MSI 0 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 8: PCI MSI 1 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 9: PCI MSI 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: MAL TX EOB */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: MAL RX EOB */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: DMA Chan 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: DMA Chan 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: DMA Chan 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: DMA Chan 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Reserved */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: Reserved */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: GPT Timer 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 19: GPT Timer 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: GPT Timer 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: GPT Timer 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: GPT Timer 4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 27: Ext Int 4 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 5 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 6 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 30: UIC1 NC Int */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 31: UIC1 Crit Int */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 32: MAL SERR */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 33: MAL TXDE */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 34: MAL RXDE */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 35: ECC Unc Err */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 36: ECC Corr Err */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 37: Ext Bus Ctrl */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 38: Ext Bus Mstr */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 39: OPB->PLB */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 40: PCI MSI 3 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 41: PCI MSI 4 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 42: PCI MSI 5 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 43: PCI MSI 6 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 44: PCI MSI 7 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 45: PCI MSI 8 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 46: PCI MSI 9 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 47: PCI MSI 10 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 48: PCI MSI 11 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 49: PLB Perf Mon */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 50: Ext Int 7 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 51: Ext Int 8 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 52: Ext Int 9 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 53: Ext Int 10 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 54: Ext Int 11 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 55: Ext Int 12 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 56: Ser ROM Err */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 57: Reserved */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 58: Reserved */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 59: PCI Async Err */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 60: EMAC 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 61: EMAC 0 WOL */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 62: EMAC 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 63: EMAC 1 WOL */ +unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */ }; -static struct ibm44x_clocks clocks __initdata; - static void __init ebony_calibrate_decr(void) { @@ -135,15 +87,10 @@ ebony_calibrate_decr(void) * on Rev. C silicon then errata forces us to * use the internal clock. */ - switch (PVR_REV(mfspr(PVR))) { - case PVR_REV(PVR_440GP_RB): - freq = EBONY_440GP_RB_SYSCLK; - break; - case PVR_REV(PVR_440GP_RC1): - default: - freq = EBONY_440GP_RC_SYSCLK; - break; - } + if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0) + freq = EBONY_440GP_RB_SYSCLK; + else + freq = EBONY_440GP_RC_SYSCLK; ibm44x_calibrate_decr(freq); } @@ -177,7 +124,7 @@ ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) } #define PCIX_WRITEL(value, offset) \ - (writel(value, (u32)pcix_reg_base+offset)) + (writel(value, pcix_reg_base + offset)) /* * FIXME: This is only here to "make it work". This will move @@ -187,9 +134,9 @@ ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) static void __init ebony_setup_pcix(void) { - void *pcix_reg_base; + void __iomem *pcix_reg_base; - pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE); + pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); /* Disable all windows */ PCIX_WRITEL(0, PCIX0_POM0SA); @@ -248,9 +195,8 @@ ebony_setup_hose(void) hose->io_space.end = EBONY_PCI_UPPER_IO; hose->mem_space.start = EBONY_PCI_LOWER_MEM; hose->mem_space.end = EBONY_PCI_UPPER_MEM; - isa_io_base = - (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE); - hose->io_base_virt = (void *)isa_io_base; + hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE); + isa_io_base = (unsigned long)hose->io_base_virt; setup_indirect_pci(hose, EBONY_PCI_CFGA_PLB32, @@ -276,47 +222,55 @@ ebony_early_serial_map(void) port.irq = 0; port.uartclk = clocks.uart0; port.regshift = 0; - port.iotype = SERIAL_IO_MEM; - port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + port.iotype = UPIO_MEM; + port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; port.line = 0; if (early_serial_setup(&port) != 0) { printk("Early serial init of port 0 failed\n"); } +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + /* Configure debug serial access */ + gen550_init(0, &port); + + /* Purge TLB entry added in head_44x.S for early serial access */ + _tlbie(UART0_IO_BASE); +#endif + port.membase = ioremap64(PPC440GP_UART1_ADDR, 8); port.irq = 1; + port.uartclk = clocks.uart1; port.line = 1; if (early_serial_setup(&port) != 0) { printk("Early serial init of port 1 failed\n"); } + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + /* Configure debug serial access */ + gen550_init(1, &port); +#endif } static void __init ebony_setup_arch(void) { - unsigned char * vpd_base; struct ocp_def *def; struct ocp_func_emac_data *emacdata; -#if !defined(CONFIG_BDI_SWITCH) - /* - * The Abatron BDI JTAG debugger does not tolerate others - * mucking with the debug registers. - */ - mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); -#endif - /* Set mac_addr for each EMAC */ - vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE); def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); emacdata = def->additions; - memcpy(emacdata->mac_addr, EBONY_NA0_ADDR(vpd_base), 6); + emacdata->phy_map = 0x00000001; /* Skip 0x00 */ + emacdata->phy_mode = PHY_MODE_RMII; + memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); + def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1); emacdata = def->additions; - memcpy(emacdata->mac_addr, EBONY_NA1_ADDR(vpd_base), 6); - iounmap(vpd_base); + emacdata->phy_map = 0x00000001; /* Skip 0x00 */ + emacdata->phy_mode = PHY_MODE_RMII; + memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); /* * Determine various clocks. @@ -353,9 +307,6 @@ ebony_setup_arch(void) ebony_early_serial_map(); - ibm4xxPIC_InitSenses = ebony_IRQ_initsenses; - ibm4xxPIC_NumInitSenses = sizeof(ebony_IRQ_initsenses); - /* Identify the system */ printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n"); } @@ -363,9 +314,7 @@ ebony_setup_arch(void) void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { - parse_bootinfo((struct bi_record *) (r3 + KERNELBASE)); - - ibm44x_platform_init(); + ibm44x_platform_init(r3, r4, r5, r6, r7); ppc_md.setup_arch = ebony_setup_arch; ppc_md.show_cpuinfo = ebony_show_cpuinfo; @@ -378,7 +327,6 @@ void __init platform_init(unsigned long r3, unsigned long r4, ppc_md.nvram_read_val = todc_direct_read_val; ppc_md.nvram_write_val = todc_direct_write_val; - #ifdef CONFIG_KGDB ppc_md.early_serial_map = ebony_early_serial_map; #endif