X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2F4xx%2Focotea.c;h=c981f70aad5f53668920b497ca4ddc5b61e5af82;hb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;hp=6376890e36c9212fa7e105947ad9d8f889b27553;hpb=a2c21200f1c81b08cb55e417b68150bba439b646;p=linux-2.6.git diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c index 6376890e3..c981f70aa 100644 --- a/arch/ppc/platforms/4xx/ocotea.c +++ b/arch/ppc/platforms/4xx/ocotea.c @@ -47,6 +47,7 @@ #include #include #include +#include #include @@ -57,27 +58,21 @@ */ #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" -extern void abort(void); +bd_t __res; + +static struct ibm44x_clocks clocks __initdata; static void __init ocotea_calibrate_decr(void) { unsigned int freq; - freq = OCOTEA_SYSCLK; - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - /* Set the time base to zero */ - mtspr(SPRN_TBWL, 0); - mtspr(SPRN_TBWU, 0); - - /* Clear any pending timer interrupts */ - mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); + if (mfspr(SPRN_CCR1) & CCR1_TCS) + freq = OCOTEA_TMR_CLK; + else + freq = clocks.cpu; - /* Enable decrementer interrupt */ - mtspr(SPRN_TCR, TCR_DIE); + ibm44x_calibrate_decr(freq); } static int @@ -88,6 +83,7 @@ ocotea_show_cpuinfo(struct seq_file *m) return 0; } + static inline int ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) { @@ -107,6 +103,46 @@ ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) return PCI_IRQ_TABLE_LOOKUP; } +static void __init ocotea_set_emacdata(void) +{ + struct ocp_def *def; + struct ocp_func_emac_data *emacdata; + int i; + + /* + * Note: Current rev. board only operates in Group 4a + * mode, so we always set EMAC0-1 for SMII and EMAC2-3 + * for RGMII (though these could run in RTBI just the same). + * + * The FPGA reg 3 information isn't even suitable for + * determining the phy_mode, so if the board becomes + * usable in !4a, it will be necessary to parse an environment + * variable from the firmware or similar to properly configure + * the phy_map/phy_mode. + */ + /* Set phy_map, phy_mode, and mac_addr for each EMAC */ + for (i=0; i<4; i++) { + def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); + emacdata = def->additions; + if (i < 2) { + emacdata->phy_map = 0x00000001; /* Skip 0x00 */ + emacdata->phy_mode = PHY_MODE_SMII; + } + else { + emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */ + emacdata->phy_mode = PHY_MODE_RGMII; + } + if (i == 0) + memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); + else if (i == 1) + memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); + else if (i == 2) + memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6); + else if (i == 3) + memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6); + } +} + #define PCIX_READW(offset) \ (readw((u32)pcix_reg_base+offset)) @@ -209,7 +245,7 @@ ocotea_setup_hose(void) TODC_ALLOC(); static void __init -ocotea_early_serial_map(const struct ibm44x_clocks *clks) +ocotea_early_serial_map(void) { struct uart_port port; @@ -217,7 +253,7 @@ ocotea_early_serial_map(const struct ibm44x_clocks *clks) memset(&port, 0, sizeof(port)); port.membase = ioremap64(PPC440GX_UART0_ADDR, 8); port.irq = UART0_INT; - port.uartclk = clks->uart0; + port.uartclk = clocks.uart0; port.regshift = 0; port.iotype = SERIAL_IO_MEM; port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; @@ -229,7 +265,7 @@ ocotea_early_serial_map(const struct ibm44x_clocks *clks) port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); port.irq = UART1_INT; - port.uartclk = clks->uart1; + port.uartclk = clocks.uart1; port.line = 1; if (early_serial_setup(&port) != 0) { @@ -240,41 +276,7 @@ ocotea_early_serial_map(const struct ibm44x_clocks *clks) static void __init ocotea_setup_arch(void) { - unsigned char *addr; - unsigned long long mac64; - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - int i; - struct ibm44x_clocks clocks; - - /* - * Note: Current rev. board only operates in Group 4a - * mode, so we always set EMAC0-1 for SMII and EMAC2-3 - * for RGMII (though these could run in RTBI just the same). - * - * The FPGA reg 3 information isn't even suitable for - * determining the phy_mode, so if the board becomes - * usable in !4a, it will be necessary to parse an environment - * variable from the firmware or similar to properly configure - * the phy_map/phy_mode. - */ - /* Set phy_map, phy_mode, and mac_addr for each EMAC */ - addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE); - for (i=0; i<4; i++) { - mac64 = simple_strtoull(addr+OCOTEA_MAC_OFFSET*i, 0, 16); - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); - emacdata = def->additions; - if (i < 2) { - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_SMII; - } - else { - emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */ - emacdata->phy_mode = PHY_MODE_RGMII; - } - memcpy(emacdata->mac_addr, (char *)&mac64+2, 6); - } - iounmap(addr); + ocotea_set_emacdata(); ibm440gx_tah_enable(); @@ -319,173 +321,33 @@ ocotea_setup_arch(void) ROOT_DEV = Root_HDA1; #endif -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif - - ocotea_early_serial_map(&clocks); + ocotea_early_serial_map(); /* Identify the system */ printk("IBM Ocotea port (MontaVista Software, Inc. )\n"); } -static void -ocotea_restart(char *cmd) -{ - local_irq_disable(); - abort(); -} - -static void -ocotea_power_off(void) -{ - local_irq_disable(); - for(;;); -} - -static void -ocotea_halt(void) -{ - local_irq_disable(); - for(;;); -} - -/* - * Read the 440GX memory controller to get size of system memory. - */ -static unsigned long __init -ocotea_find_end_of_memory(void) -{ - u32 i, bank_config; - u32 mem_size = 0; - - for (i=0; i<4; i++) - { - switch (i) - { - case 0: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR); - break; - case 1: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR); - break; - case 2: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR); - break; - case 3: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR); - break; - } - - bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); - - if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE)) - continue; - switch (SDRAM_CONFIG_BANK_SIZE(bank_config)) - { - case SDRAM_CONFIG_SIZE_8M: - mem_size += PPC44x_MEM_SIZE_8M; - break; - case SDRAM_CONFIG_SIZE_16M: - mem_size += PPC44x_MEM_SIZE_16M; - break; - case SDRAM_CONFIG_SIZE_32M: - mem_size += PPC44x_MEM_SIZE_32M; - break; - case SDRAM_CONFIG_SIZE_64M: - mem_size += PPC44x_MEM_SIZE_64M; - break; - case SDRAM_CONFIG_SIZE_128M: - mem_size += PPC44x_MEM_SIZE_128M; - break; - case SDRAM_CONFIG_SIZE_256M: - mem_size += PPC44x_MEM_SIZE_256M; - break; - case SDRAM_CONFIG_SIZE_512M: - mem_size += PPC44x_MEM_SIZE_512M; - break; - } - } - return mem_size; -} - -static void __init -ocotea_init_irq(void) -{ - int i; - - ppc4xx_pic_init(); - - for (i = 0; i < NR_IRQS; i++) - irq_desc[i].handler = ppc4xx_pic; -} - -#ifdef CONFIG_SERIAL_TEXT_DEBUG -#include -#include -#include -struct serial_state rs_table[RS_TABLE_SIZE] = { - SERIAL_PORT_DFNS /* Defined in */ -}; - -static void -ocotea_progress(char *s, unsigned short hex) -{ - volatile char c; - volatile unsigned long com_port; - u16 shift; - - com_port = (unsigned long)rs_table[0].iomem_base; - shift = rs_table[0].iomem_reg_shift; - - while ((c = *s++) != 0) { - while ((*((volatile unsigned char *)com_port + - (UART_LSR << shift)) & UART_LSR_THRE) == 0) - ; - *(volatile unsigned char *)com_port = c; - - } - - /* Send LF/CR to pretty up output */ - while ((*((volatile unsigned char *)com_port + - (UART_LSR << shift)) & UART_LSR_THRE) == 0) - ; - *(volatile unsigned char *)com_port = '\r'; - while ((*((volatile unsigned char *)com_port + - (UART_LSR << shift)) & UART_LSR_THRE) == 0) - ; - *(volatile unsigned char *)com_port = '\n'; -} -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ - -#if 0 -static void __init -ocotea_map_io(void) -{ - io_block_mapping(0xe0000000, 0x0000000140000000, - 0x00001000, _PAGE_IO); -} -#endif - void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { - parse_bootinfo((struct bi_record *) (r3 + KERNELBASE)); + parse_bootinfo(find_bootinfo()); + + /* + * If we were passed in a board information, copy it into the + * residual data area. + */ + if (r3) + __res = *(bd_t *)(r3 + KERNELBASE); /* Disable L2-Cache due to hardware issues */ ibm440gx_l2c_disable(); + ibm44x_platform_init(); + ppc_md.setup_arch = ocotea_setup_arch; ppc_md.show_cpuinfo = ocotea_show_cpuinfo; - ppc_md.init_IRQ = ocotea_init_irq; ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - ppc_md.find_end_of_memory = ocotea_find_end_of_memory; - - ppc_md.restart = ocotea_restart; - ppc_md.power_off = ocotea_power_off; - ppc_md.halt = ocotea_halt; - ppc_md.calibrate_decr = ocotea_calibrate_decr; ppc_md.time_init = todc_time_init; ppc_md.set_rtc_time = todc_set_rtc_time; @@ -494,9 +356,6 @@ void __init platform_init(unsigned long r3, unsigned long r4, ppc_md.nvram_read_val = todc_direct_read_val; ppc_md.nvram_write_val = todc_direct_write_val; -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = ocotea_progress; -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ #ifdef CONFIG_KGDB ppc_md.early_serial_map = ocotea_early_serial_map; #endif