X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2F85xx%2Fmpc8560_ads.c;h=3a060468dd950ae8102567de4c0c278d23a722c6;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=0cb2c34588cd3aef0e87efcdaf9cbe916c3a2af5;hpb=5fc42a6ed0ec81088c37caadb45898ae6cd0ad2c;p=linux-2.6.git diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c index 0cb2c3458..3a060468d 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.c +++ b/arch/ppc/platforms/85xx/mpc8560_ads.c @@ -1,9 +1,7 @@ /* - * arch/ppc/platforms/85xx/mpc8560_ads.c - * * MPC8560ADS board specific routines * - * Maintainer: Kumar Gala + * Maintainer: Kumar Gala * * Copyright 2004 Freescale Semiconductor Inc. * @@ -13,7 +11,6 @@ * option) any later version. */ -#include #include #include #include @@ -24,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -32,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -40,7 +38,6 @@ #include #include #include -#include #include #include #include @@ -48,7 +45,7 @@ #include #include #include -#include +#include #include #include @@ -56,49 +53,86 @@ #include #include -extern void cpm2_reset(void); - -struct ocp_gfar_data mpc85xx_tsec1_def = { - .interruptTransmit = MPC85xx_IRQ_TSEC1_TX, - .interruptError = MPC85xx_IRQ_TSEC1_ERROR, - .interruptReceive = MPC85xx_IRQ_TSEC1_RX, - .interruptPHY = MPC85xx_IRQ_EXT5, - .flags = (GFAR_HAS_GIGABIT | GFAR_HAS_MULTI_INTR - | GFAR_HAS_RMON | GFAR_HAS_COALESCE - | GFAR_HAS_PHY_INTR), - .phyid = 0, - .phyregidx = 0, -}; - -struct ocp_gfar_data mpc85xx_tsec2_def = { - .interruptTransmit = MPC85xx_IRQ_TSEC2_TX, - .interruptError = MPC85xx_IRQ_TSEC2_ERROR, - .interruptReceive = MPC85xx_IRQ_TSEC2_RX, - .interruptPHY = MPC85xx_IRQ_EXT5, - .flags = (GFAR_HAS_GIGABIT | GFAR_HAS_MULTI_INTR - | GFAR_HAS_RMON | GFAR_HAS_COALESCE - | GFAR_HAS_PHY_INTR), - .phyid = 1, - .phyregidx = 0, -}; - -struct ocp_fs_i2c_data mpc85xx_i2c1_def = { - .flags = FS_I2C_SEPARATE_DFSRR, -}; /* ************************************************************************ * * Setup the architecture * */ +static void init_fcc_ioports(void) +{ + struct immap *immap; + struct io_port *io; + u32 tempval; + + immap = cpm2_immr; + + io = &immap->im_ioport; + /* FCC2/3 are on the ports B/C. */ + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB2_DIRB0; + tempval |= PB2_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB2_PSORB0; + tempval |= PB2_PSORB1; + out_be32(&io->iop_psorb, tempval); + + tempval = in_be32(&io->iop_pparb); + tempval |= (PB2_DIRB0 | PB2_DIRB1); + out_be32(&io->iop_pparb, tempval); + + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB3_DIRB0; + tempval |= PB3_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB3_PSORB0; + tempval |= PB3_PSORB1; + out_be32(&io->iop_psorb, tempval); + + tempval = in_be32(&io->iop_pparb); + tempval |= (PB3_DIRB0 | PB3_DIRB1); + out_be32(&io->iop_pparb, tempval); + + tempval = in_be32(&io->iop_pdirc); + tempval |= PC3_DIRC1; + out_be32(&io->iop_pdirc, tempval); + + tempval = in_be32(&io->iop_pparc); + tempval |= PC3_DIRC1; + out_be32(&io->iop_pparc, tempval); + + /* Port C has clocks...... */ + tempval = in_be32(&io->iop_psorc); + tempval &= ~(CLK_TRX); + out_be32(&io->iop_psorc, tempval); + + tempval = in_be32(&io->iop_pdirc); + tempval &= ~(CLK_TRX); + out_be32(&io->iop_pdirc, tempval); + tempval = in_be32(&io->iop_pparc); + tempval |= (CLK_TRX); + out_be32(&io->iop_pparc, tempval); + + /* Configure Serial Interface clock routing. + * First, clear all FCC bits to zero, + * then set the ones we want. + */ + immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK); + immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE; +} static void __init mpc8560ads_setup_arch(void) { - struct ocp_def *def; - struct ocp_gfar_data *einfo; bd_t *binfo = (bd_t *) __res; unsigned int freq; + struct gianfar_platform_data *pdata; + struct gianfar_mdio_data *mdata; + struct fs_platform_info *fpi; cpm2_reset(); @@ -117,16 +151,52 @@ mpc8560ads_setup_arch(void) mpc85xx_setup_hose(); #endif - def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 0); - if (def) { - einfo = (struct ocp_gfar_data *) def->additions; - memcpy(einfo->mac_addr, binfo->bi_enetaddr, 6); + /* setup the board related info for the MDIO bus */ + mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); + + mdata->irq[0] = MPC85xx_IRQ_EXT5; + mdata->irq[1] = MPC85xx_IRQ_EXT5; + mdata->irq[2] = PHY_POLL; + mdata->irq[3] = MPC85xx_IRQ_EXT5; + mdata->irq[31] = PHY_POLL; + + /* setup the board related information for the enet controllers */ + pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); + if (pdata) { + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; + pdata->bus_id = 0; + pdata->phy_id = 0; + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } - def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 1); - if (def) { - einfo = (struct ocp_gfar_data *) def->additions; - memcpy(einfo->mac_addr, binfo->bi_enet1addr, 6); + pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); + if (pdata) { + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; + pdata->bus_id = 0; + pdata->phy_id = 1; + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); + } + + init_fcc_ioports(); + ppc_sys_device_remove(MPC85xx_CPM_FCC1); + + fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2); + if (fpi) { + memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); + fpi->bus_id = "0:02"; + fpi->phy_addr = 2; + fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; + fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1]; + } + + fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3); + if (fpi) { + memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); + fpi->macaddr[5] += 1; + fpi->bus_id = "0:03"; + fpi->phy_addr = 3; + fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; + fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2]; } #ifdef CONFIG_BLK_DEV_INITRD @@ -139,42 +209,32 @@ mpc8560ads_setup_arch(void) #else ROOT_DEV = Root_HDA1; #endif - - ocp_for_each_device(mpc85xx_update_paddr_ocp, &(binfo->bi_immr_base)); } -static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) +static irqreturn_t cpm2_cascade(int irq, void *dev_id) { - while ((irq = cpm2_get_irq(regs)) >= 0) { - ppc_irq_dispatch_handler(regs, irq); - } + while ((irq = cpm2_get_irq()) >= 0) + __do_IRQ(irq); return IRQ_HANDLED; } +static struct irqaction cpm2_irqaction = { + .handler = cpm2_cascade, + .flags = IRQF_DISABLED, + .mask = CPU_MASK_NONE, + .name = "cpm2_cascade", +}; + static void __init mpc8560_ads_init_IRQ(void) { - int i; - volatile cpm2_map_t *immap = cpm2_immr; - /* Setup OpenPIC */ mpc85xx_ads_init_IRQ(); - /* disable all CPM interupts */ - immap->im_intctl.ic_simrh = 0x0; - immap->im_intctl.ic_simrl = 0x0; - - for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++) - irq_desc[i].handler = &cpm2_pic; + /* Setup CPM2 PIC */ + cpm2_init_IRQ(); - /* Initialize the default interrupt mapping priorities, - * in case the boot rom changed something on us. - */ - immap->im_intctl.ic_sicr = 0; - immap->im_intctl.ic_scprrh = 0x05309770; - immap->im_intctl.ic_scprrl = 0x05309770; - - request_irq(MPC85xx_IRQ_CPM, cpm2_cascade, SA_INTERRUPT, "cpm2_cascade", NULL); + setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); return; } @@ -216,6 +276,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, strcpy(cmd_line, (char *) (r6 + KERNELBASE)); } + identify_ppc_sys_by_id(mfspr(SPRN_SVR)); + /* setup the PowerPC module struct */ ppc_md.setup_arch = mpc8560ads_setup_arch; ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;