X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2F85xx%2Fmpc85xx_cds_common.c;h=a65eb0225d564d06ff4b20595ec870a87da2a693;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=5eb6e4218111c7353eef1f0208114420168ceefa;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index 5eb6e4218..a65eb0225 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -48,7 +49,7 @@ #include #include #include -#include +#include #include #include @@ -129,32 +130,6 @@ static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { #endif }; -struct ocp_gfar_data mpc85xx_tsec1_def = { - .interruptTransmit = MPC85xx_IRQ_TSEC1_TX, - .interruptError = MPC85xx_IRQ_TSEC1_ERROR, - .interruptReceive = MPC85xx_IRQ_TSEC1_RX, - .interruptPHY = MPC85xx_IRQ_EXT5, - .flags = (GFAR_HAS_GIGABIT | GFAR_HAS_MULTI_INTR | - GFAR_HAS_PHY_INTR), - .phyid = 0, - .phyregidx = 0, -}; - -struct ocp_gfar_data mpc85xx_tsec2_def = { - .interruptTransmit = MPC85xx_IRQ_TSEC2_TX, - .interruptError = MPC85xx_IRQ_TSEC2_ERROR, - .interruptReceive = MPC85xx_IRQ_TSEC2_RX, - .interruptPHY = MPC85xx_IRQ_EXT5, - .flags = (GFAR_HAS_GIGABIT | GFAR_HAS_MULTI_INTR | - GFAR_HAS_PHY_INTR), - .phyid = 1, - .phyregidx = 0, -}; - -struct ocp_fs_i2c_data mpc85xx_i2c1_def = { - .flags = FS_I2C_SEPARATE_DFSRR, -}; - /* ************************************************************************ */ int mpc85xx_cds_show_cpuinfo(struct seq_file *m) @@ -172,8 +147,7 @@ mpc85xx_cds_show_cpuinfo(struct seq_file *m) seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]); - seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000, - freq % 1000000); + seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); seq_printf(m, "PVR\t\t: 0x%x\n", pvid); seq_printf(m, "SVR\t\t: 0x%x\n", svid); @@ -191,10 +165,15 @@ mpc85xx_cds_show_cpuinfo(struct seq_file *m) static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) { while((irq = cpm2_get_irq(regs)) >= 0) - { - ppc_irq_dispatch_handler(regs,irq); - } + __do_IRQ(irq, regs); } + +static struct irqaction cpm2_irqaction = { + .handler = cpm2_cascade, + .flags = SA_INTERRUPT, + .mask = CPU_MASK_NONE, + .name = "cpm2_cascade", +}; #endif /* CONFIG_CPM2 */ void __init @@ -237,7 +216,7 @@ mpc85xx_cds_init_IRQ(void) immap->im_intctl.ic_scprrh = 0x05309770; immap->im_intctl.ic_scprrl = 0x05309770; - request_irq(MPC85xx_IRQ_CPM, cpm2_cascade, SA_INTERRUPT, "cpm2_cascade", NULL); + setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); #endif return; @@ -302,16 +281,17 @@ mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) #define ARCADIA_HOST_BRIDGE_IDSEL 17 #define ARCADIA_2ND_BRIDGE_IDSEL 3 +extern int mpc85xx_pci1_last_busno; + int mpc85xx_exclude_device(u_char bus, u_char devfn) { if (bus == 0 && PCI_SLOT(devfn) == 0) return PCIBIOS_DEVICE_NOT_FOUND; #ifdef CONFIG_85xx_PCI2 - /* With the current code we know PCI2 will be bus 2, however this may - * not be guarnteed */ - if (bus == 2 && PCI_SLOT(devfn) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; + if (mpc85xx_pci1_last_busno) + if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; #endif /* We explicitly do not go past the Tundra 320 Bridge */ if (bus == 1) @@ -331,10 +311,9 @@ mpc85xx_exclude_device(u_char bus, u_char devfn) static void __init mpc85xx_cds_setup_arch(void) { - struct ocp_def *def; - struct ocp_gfar_data *einfo; bd_t *binfo = (bd_t *) __res; unsigned int freq; + struct gianfar_platform_data *pdata; /* get the core frequency */ freq = binfo->bi_intfreq; @@ -368,17 +347,23 @@ mpc85xx_cds_setup_arch(void) invalidate_tlbcam_entry(NUM_TLBCAMS - 1); #endif - def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 0); - if (def) { - einfo = (struct ocp_gfar_data *) def->additions; - memcpy(einfo->mac_addr, binfo->bi_enetaddr, 6); - } + /* setup the board related information for the enet controllers */ + pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; + pdata->interruptPHY = MPC85xx_IRQ_EXT5; + pdata->phyid = 0; + /* fixup phy address */ + pdata->phy_reg_addr += binfo->bi_immr_base; + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); + + pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; + pdata->interruptPHY = MPC85xx_IRQ_EXT5; + pdata->phyid = 1; + /* fixup phy address */ + pdata->phy_reg_addr += binfo->bi_immr_base; + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); - def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 1); - if (def) { - einfo = (struct ocp_gfar_data *) def->additions; - memcpy(einfo->mac_addr, binfo->bi_enet1addr, 6); - } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) @@ -390,8 +375,6 @@ mpc85xx_cds_setup_arch(void) #else ROOT_DEV = Root_HDA1; #endif - - ocp_for_each_device(mpc85xx_update_paddr_ocp, &(binfo->bi_immr_base)); } /* ************************************************************************ */ @@ -414,11 +397,25 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, #ifdef CONFIG_SERIAL_TEXT_DEBUG { bd_t *binfo = (bd_t *) __res; + struct uart_port p; /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base, - binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); + binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); + + memset(&p, 0, sizeof (p)); + p.iotype = SERIAL_IO_MEM; + p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET; + p.uartclk = binfo->bi_busfreq; + + gen550_init(0, &p); + memset(&p, 0, sizeof (p)); + p.iotype = SERIAL_IO_MEM; + p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET; + p.uartclk = binfo->bi_busfreq; + + gen550_init(1, &p); } #endif @@ -440,6 +437,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, strcpy(cmd_line, (char *) (r6 + KERNELBASE)); } + identify_ppc_sys_by_id(mfspr(SVR)); + /* setup the PowerPC module struct */ ppc_md.setup_arch = mpc85xx_cds_setup_arch; ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;