X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fchestnut.c;h=f324f757cae16fe3dda87278f91f31bd5ee22a3d;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=502291e4c31502131d2e66ad138fa4e99d250592;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git diff --git a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c index 502291e4c..f324f757c 100644 --- a/arch/ppc/platforms/chestnut.c +++ b/arch/ppc/platforms/chestnut.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chestnut.c - * * Board setup routines for IBM Chestnut * * Author: @@ -28,13 +26,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include @@ -42,8 +40,8 @@ #include #include -static u32 boot_base; /* Virtual addr of 8bit boot */ -static u32 cpld_base; /* Virtual addr of CPLD Regs */ +static void __iomem *sram_base; /* Virtual addr of Internal SRAM */ +static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */ static mv64x60_handle_t bh; @@ -65,7 +63,8 @@ extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh); * ****/ static void __init -chestnut_calibrate_decr(void){ +chestnut_calibrate_decr(void) +{ ulong freq; freq = CHESTNUT_BUS_SPEED / 4; @@ -75,8 +74,6 @@ chestnut_calibrate_decr(void){ tb_ticks_per_jiffy = freq / HZ; tb_to_us = mulhwu_scale_factor(freq, 1000000); - - return; } static int @@ -103,7 +100,7 @@ chestnut_find_end_of_memory(void) mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, MV64x60_TYPE_MV64460); } - return(mem_size); + return mem_size; } #if defined(CONFIG_SERIAL_8250) @@ -117,7 +114,7 @@ chestnut_early_serial_map(void) port.uartclk = BASE_BAUD * 16; port.irq = UART0_INT; port.flags = STD_COM_FLAGS | UPF_IOREMAP; - port.iotype = SERIAL_IO_MEM; + port.iotype = UPIO_MEM; port.mapbase = CHESTNUT_UART0_IO_BASE; port.regshift = 0; @@ -155,7 +152,7 @@ chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) }; const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return (PCI_IRQ_TABLE_LOOKUP); + return PCI_IRQ_TABLE_LOOKUP; } @@ -193,24 +190,30 @@ chestnut_setup_bridge(void) si.pci_0.pci_cmd_bits = 0; si.pci_0.latency_timer = 0x80; - si.window_preserve_mask_32_lo = CHESTNUT_PRESERVE_MASK; - for (i=0; ifirst_busno = 0; bh.hose_a->last_busno = 0xff; bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); - } void __init chestnut_setup_peripherals(void) { - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); + mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); + cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); + mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0); - /* Set up window for internal sram (256KByte insize) */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); - boot_base = (u32)ioremap(CHESTNUT_BOOT_8BIT_BASE, - CHESTNUT_BOOT_8BIT_SIZE); - cpld_base = (u32)ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE); + mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, + CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - /* - * Configure internal SRAM - - * Cache coherent write back, incase - * CONFIG_MV64360_SRAM_CACHE_COHERENT set - * Parity enabled. - * Parity error propagation - * Arbitration not parked for CPU only - * Other bits are reserved. - */ -#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); -#else +#ifdef CONFIG_NOT_COHERENT_CACHE mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0); +#else + mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); #endif + sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); + memset(sram_base, 0, MV64360_SRAM_SIZE); - /* - * Setting the SRAM to 0. Note that this generates parity errors on - * internal data path in SRAM since it's first time accessing it - * while after reset it's not configured - */ - memset((void *)CHESTNUT_INTERNAL_SRAM_BASE, 0, CHESTNUT_INTERNAL_SRAM_SIZE); /* * Configure MPP pins for PCI DMA * @@ -312,9 +304,9 @@ chestnut_setup_peripherals(void) (0xf << 20) | /* MPPSel13 GPIO[13] */ (0xf << 24) | /* MPPSel14 GPIO[14] */ (0xf << 28)); /* MPPSel15 GPIO[15] */ - mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, + mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */ BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | - BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* Output */ + BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* * Configure the following MPP pins to indicate a level @@ -364,7 +356,7 @@ chestnut_setup_peripherals(void) /* * Dismiss and then enable interrupt on CPU #0 high cause register * BIT27 summarizes GPP interrupts 24-31 - */ + */ mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27)); if (ppc_md.progress) @@ -423,14 +415,32 @@ chestnut_setup_arch(void) /* Identify the system */ printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n"); - printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc. (source@mvista.com)\n"); + printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc." + " (source@mvista.com)\n"); if (ppc_md.progress) ppc_md.progress("chestnut_setup_arch: exit", 0); +} - return; +#ifdef CONFIG_MTD_PHYSMAP +static struct mtd_partition ptbl; + +static int __init +chestnut_setup_mtd(void) +{ + memset(&ptbl, 0, sizeof(ptbl)); + + ptbl.name = "User FS"; + ptbl.size = CHESTNUT_32BIT_SIZE; + + physmap_map.size = CHESTNUT_32BIT_SIZE; + physmap_set_partitions(&ptbl, 1); + return 0; } +arch_initcall(chestnut_setup_mtd); +#endif + /************************************************************************** * FUNCTION: chestnut_restart * @@ -450,7 +460,7 @@ chestnut_restart(char *cmd) * * MPP24 - board reset */ - writeb(0x1, (void __iomem *)(cpld_base+3)); + writeb(0x1, cpld_base + 3); /* GPP pin tied to MPP earlier */ mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24)); @@ -474,37 +484,6 @@ chestnut_power_off(void) /* NOTREACHED */ } -#define SET_PCI_COMMAND_INVALIDATE -#ifdef SET_PCI_COMMAND_INVALIDATE -/* - * Dave Wilhardt found that PCI_COMMAND_INVALIDATE must - * be set for each device if you are using cache coherency. - */ -static void __init -set_pci_command_invalidate(void) -{ - struct pci_dev *dev = NULL; - u16 val; - - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - pci_read_config_word(dev, PCI_COMMAND, &val); - val |= PCI_COMMAND_INVALIDATE; - pci_write_config_word(dev, PCI_COMMAND, val); - - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, - L1_CACHE_LINE_SIZE >> 2); - } -} -#endif - -static void __init -chestnut_pci_fixups(void) -{ -#ifdef SET_PCI_COMMAND_INVALIDATE - set_pci_command_invalidate(); -#endif -} - /************************************************************************** * FUNCTION: chestnut_map_io * @@ -514,27 +493,9 @@ chestnut_pci_fixups(void) static void __init chestnut_map_io(void) { -#ifdef CONFIG_MV64360_SRAM_CACHEABLE - io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_SIZE, - _PAGE_KERNEL | _PAGE_GUARDED); -#else -#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT - io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_SIZE, - _PAGE_KERNEL | _PAGE_GUARDED | _PAGE_COHERENT); -#else - io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_BASE, - CHESTNUT_INTERNAL_SRAM_SIZE, - _PAGE_IO); -#endif /* !CONFIG_MV64360_SRAM_CACHE_COHERENT */ -#endif /* !CONFIG_MV64360_SRAM_CACHEABLE */ - #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, _PAGE_IO); + io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, + _PAGE_IO); #endif } @@ -549,11 +510,9 @@ static __inline__ void chestnut_set_bat(void) { mb(); - mtspr(DBAT3U, 0xf0001ffe); - mtspr(DBAT3L, 0xf000002a); + mtspr(SPRN_DBAT3U, 0xf0001ffe); + mtspr(SPRN_DBAT3L, 0xf000002a); mb(); - - return; } /************************************************************************** @@ -580,14 +539,12 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.setup_arch = chestnut_setup_arch; ppc_md.show_cpuinfo = chestnut_show_cpuinfo; - ppc_md.irq_canonicalize = NULL; ppc_md.init_IRQ = mv64360_init_irq; ppc_md.get_irq = mv64360_get_irq; ppc_md.init = NULL; ppc_md.find_end_of_memory = chestnut_find_end_of_memory; ppc_md.setup_io_mappings = chestnut_map_io; - ppc_md.pcibios_fixup = chestnut_pci_fixups; ppc_md.restart = chestnut_restart; ppc_md.power_off = chestnut_power_off; @@ -603,8 +560,6 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.heartbeat = NULL; - ppc_md.pcibios_fixup = chestnut_pci_fixups; - bh.p_base = CONFIG_MV64X60_NEW_BASE; chestnut_set_bat(); @@ -618,6 +573,4 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, if (ppc_md.progress) ppc_md.progress("chestnut_init(): exit", 0); - - return; }