X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fev64260.c;h=29d494dce2148eafd8189ca2de67dccb20e9051a;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=127588904a51dbd9298a6df751c1d9fa8cd0f63c;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c index 127588904..29d494dce 100644 --- a/arch/ppc/platforms/ev64260.c +++ b/arch/ppc/platforms/ev64260.c @@ -37,34 +37,25 @@ #include #include #include +#else +#include #endif #include #include #include -#include #include #include -#include #include #define BOARD_VENDOR "Marvell/Galileo" #define BOARD_MACHINE "EV-64260-BP" -/* Set IDE controllers into Native mode? */ -/* XXXX -#define SET_PCI_IDE_NATIVE -*/ - -ulong ev64260_mem_size = 0; -bd_t ppcboot_bd; -int ppcboot_bd_valid=0; - -static mv64x60_handle_t bh; +static struct mv64x60_handle bh; #if !defined(CONFIG_SERIAL_MPSC_CONSOLE) extern void gen550_progress(char *, unsigned short); -extern void gen550_init(int, struct serial_struct *); +extern void gen550_init(int, struct uart_port *); #endif static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */ @@ -81,16 +72,7 @@ TODC_ALLOC(); static int ev64260_get_bus_speed(void) { - int speed; - - if (ppcboot_bd_valid) { - speed = ppcboot_bd.bi_busfreq; - } - else { - speed = 100000000; /* Only 100MHz is stable */ - } - - return speed; + return 100000000; } static int @@ -114,53 +96,10 @@ ev64260_get_cpu_speed(void) unsigned long __init ev64260_find_end_of_memory(void) { - if(!ppcboot_bd_valid) { - return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_GT64260A); - } - return ppcboot_bd.bi_memsize; + return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, + MV64x60_TYPE_GT64260A); } -#if 0 /* XXXX */ -#ifdef SET_PCI_IDE_NATIVE -static void __init -set_pci_native_mode(void) -{ - struct pci_dev *dev; - - /* Better way of doing this ??? */ - pci_for_each_dev(dev) { - int class = dev->class >> 8; - - /* enable pci native mode */ - if (class == PCI_CLASS_STORAGE_IDE) { - u8 reg; - - pci_read_config_byte(dev, 0x9, ®); - if (reg == 0x8a) { - printk("PCI: Enabling PCI IDE native mode on %s\n", dev->slot_name); - pci_write_config_byte(dev, 0x9, 0x8f); - - /* let the pci code set this device up after we change it */ - pci_setup_device(dev); - } else if (reg != 0x8f) { - printk("PCI: IDE chip in unknown mode 0x%02x on %s", reg, dev->slot_name); - } - } - } -} -#endif -#endif - -static void __init -ev64260_pci_fixups(void) -{ -#ifdef SET_PCI_IDE_NATIVE - set_pci_native_mode(); -#endif -} - - /* * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing. * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first @@ -175,7 +114,7 @@ ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) if (hose->index == 0) { static char pci_irq_table[][4] = /* - * PCI IDSEL/INTPIN->INTLINE + * PCI IDSEL/INTPIN->INTLINE * A B C D */ { @@ -189,7 +128,7 @@ ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) else { static char pci_irq_table[][4] = /* - * PCI IDSEL/INTPIN->INTLINE + * PCI IDSEL/INTPIN->INTLINE * A B C D */ { @@ -207,27 +146,31 @@ ev64260_setup_peripherals(void) { mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, EV64260_TODC_BASE, EV64260_TODC_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, EV64260_UART_BASE, EV64260_UART_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); TODC_INIT(TODC_TYPE_DS1501, 0, 0, ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8); - mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG, ((1<<28) | (1<<29))); + mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29))); mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27)); - if (ev64260_get_bus_speed() > 100000000) { + if (ev64260_get_bus_speed() > 100000000) mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23)); - } - mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL,((1<<0) | (1<<3))); - mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL,((1<<0) | (1<<3))); + mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); + mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); /* * Enabling of PCI internal-vs-external arbitration @@ -240,6 +183,22 @@ ev64260_setup_peripherals(void) mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */ + /* + * Turn off timer/counters. Not turning off watchdog timer because + * can't read its reg on the 64260A so don't know if we'll be enabling + * or disabling. + */ + mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, + ((1<<0) | (1<<8) | (1<<16) | (1<<24))); + mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL, + ((1<<0) | (1<<8) | (1<<16) | (1<<24))); + + /* + * Set MPSC Multiplex RMII + * NOTE: ethernet driver modifies bit 0 and 1 + */ + mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102); + /* * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260 * bridge as interrupt inputs (via the General Purpose Ports (GPP) @@ -258,8 +217,7 @@ ev64260_setup_peripherals(void) * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0 * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0 */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, - (0xf<<8) | (0xf<<12) | (0xf<<20)); + mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20)); #define GPP_EXTERNAL_INTERRUPTS \ ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29)) @@ -272,75 +230,44 @@ ev64260_setup_peripherals(void) mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS); mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS); - /* - * Set MPSC Multiplex RMII - * NOTE: ethernet driver modifies bit 0 and 1 - */ - mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102); return; } - static void __init ev64260_setup_bridge(void) { - mv64x60_setup_info_t si; - int i; + struct mv64x60_setup_info si; + int i; memset(&si, 0, sizeof(si)); si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - si.map_irq = ev64260_map_irq; si.pci_0.enable_bus = 1; - si.pci_0.enumerate_bus = 1; - si.pci_0.pci_io.cpu_base = 0xa0000000; + si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE; si.pci_0.pci_io.pci_base_hi = 0; - si.pci_0.pci_io.pci_base_lo = 0; - si.pci_0.pci_io.size = 0x01000000; - si.pci_0.pci_io.swap = 0x01000000; /* XXXX No swapping */ - si.pci_0.pci_mem[0].cpu_base = 0x80000000; + si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE; + si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE; + si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; + si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE; si.pci_0.pci_mem[0].pci_base_hi = 0; - si.pci_0.pci_mem[0].pci_base_lo = 0x80000000; - si.pci_0.pci_mem[0].size = 0x10000000; - si.pci_0.pci_mem[0].swap = 0x01000000; /* XXXX No swapping */ - si.pci_0.pci_mem[1].cpu_base = 0; - si.pci_0.pci_mem[1].pci_base_hi = 0; - si.pci_0.pci_mem[1].pci_base_lo = 0; - si.pci_0.pci_mem[1].size = 0; /* Don't use this window */ - si.pci_0.pci_mem[1].swap = 0; - si.pci_0.pci_mem[2].cpu_base = 0; - si.pci_0.pci_mem[2].pci_base_hi = 0; - si.pci_0.pci_mem[2].pci_base_lo = 0; - si.pci_0.pci_mem[2].size = 0; /* Don't use this window */ - si.pci_0.pci_mem[1].swap = 0; + si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE; + si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE; + si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; si.pci_0.pci_cmd_bits = 0; si.pci_0.latency_timer = 0x8; si.pci_1.enable_bus = 1; - si.pci_1.enumerate_bus = 1; - si.pci_1.pci_io.cpu_base = 0xa1000000; + si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE; si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = 0x01000000; - si.pci_1.pci_io.size = 0x01000000; - si.pci_1.pci_io.swap = 0x01000000; /* XXXX No swapping */ - si.pci_1.pci_mem[0].cpu_base = 0x90000000; + si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE; + si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE; + si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; + si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE; si.pci_1.pci_mem[0].pci_base_hi = 0; - si.pci_1.pci_mem[0].pci_base_lo = 0x90000000; - si.pci_1.pci_mem[0].size = 0x10000000; - si.pci_1.pci_mem[0].swap = 0x01000000; /* XXXX No swapping */ - si.pci_1.pci_mem[1].cpu_base = 0; - si.pci_1.pci_mem[1].pci_base_hi = 0; - si.pci_1.pci_mem[1].pci_base_lo = 0; - si.pci_1.pci_mem[1].size = 0; /* Don't use this window */ - si.pci_1.pci_mem[1].swap = 0; - si.pci_1.pci_mem[2].cpu_base = 0; - si.pci_1.pci_mem[2].pci_base_hi = 0; - si.pci_1.pci_mem[2].pci_base_lo = 0; - si.pci_1.pci_mem[2].size = 0; /* Don't use this window */ - si.pci_1.pci_mem[1].swap = 0; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x8; + si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE; + si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE; + si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; si.pci_1.pci_cmd_bits = 0; si.pci_1.latency_timer = 0x8; @@ -348,9 +275,6 @@ ev64260_setup_bridge(void) si.cpu_prot_options[i] = 0; si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB; si.pci_0.acc_cntl_options[i] = - /* Breaks PCI (especially slot 4) - GT64260_PCI_ACC_CNTL_PREFETCHEN | - */ GT64260_PCI_ACC_CNTL_DREADEN | GT64260_PCI_ACC_CNTL_RDPREFETCH | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH | @@ -359,9 +283,6 @@ ev64260_setup_bridge(void) GT64260_PCI_ACC_CNTL_MBURST_32_BTYES; si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB; si.pci_1.acc_cntl_options[i] = - /* Breaks PCI (especially slot 4) - GT64260_PCI_ACC_CNTL_PREFETCHEN | - */ GT64260_PCI_ACC_CNTL_DREADEN | GT64260_PCI_ACC_CNTL_RDPREFETCH | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH | @@ -372,9 +293,24 @@ ev64260_setup_bridge(void) } /* Lookup PCI host bridges */ - if (mv64x60_init(&bh, &si)) { - printk("Bridge initialization failed.\n"); - } + if (mv64x60_init(&bh, &si)) + printk(KERN_ERR "Bridge initialization failed.\n"); + + pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */ + ppc_md.pci_swizzle = common_swizzle; + ppc_md.pci_map_irq = ev64260_map_irq; + ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; + + mv64x60_set_bus(&bh, 0, 0); + bh.hose_a->first_busno = 0; + bh.hose_a->last_busno = 0xff; + bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); + + bh.hose_b->first_busno = bh.hose_a->last_busno + 1; + mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); + bh.hose_b->last_busno = 0xff; + bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, + bh.hose_b->first_busno); return; } @@ -400,23 +336,9 @@ ev64260_early_serial_map(void) gen550_init(0, &port); #endif - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - -#if 0 /* XXXX */ - /* Assume early_serial_setup() doesn't modify port */ - port.membase = ioremap(EV64260_SERIAL_1, EV64260_UART_SIZE); - port.irq = EV64260_UART_1_IRQ; - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - gen550_init(1, &port); -#endif - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } -#endif + if (early_serial_setup(&port) != 0) + printk(KERN_WARNING "Early serial init of port 0" + "failed\n"); first_time = 0; } @@ -427,63 +349,13 @@ ev64260_early_serial_map(void) static void __init ev64260_early_serial_map(void) { -#ifdef CONFIG_KGDB - static char first_time = 1; - - -#if defined(CONFIG_KGDB_TTYS0) -#define KGDB_PORT 0 -#elif defined(CONFIG_KGDB_TTYS1) -#define KGDB_PORT 1 -#else -#error "Invalid kgdb_tty port" -#endif - - if (first_time) { - gt_early_mpsc_init(KGDB_PORT, B9600|CS8|CREAD|HUPCL|CLOCAL); - first_time = 0; - } - - return; -#endif } #endif -static void __init -ev64260_fixup_ocp(void) -{ -#if defined(CONFIG_SERIAL_MPSC) - struct ocp_device *dev; - mv64x60_ocp_mpsc_data_t *dp; - - if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 0)) - != NULL) { - dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions; - - dp->max_idle = 40; /* XXXX what should this be? */ - dp->default_baud = EV64260_DEFAULT_BAUD; - dp->brg_clk_src = EV64260_MPSC_CLK_SRC; - dp->brg_clk_freq = EV64260_MPSC_CLK_FREQ; - } - - if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 1)) - != NULL) { - dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions; - - dp->max_idle = 40; /* XXXX what should this be? */ - dp->default_baud = 9600; /* XXXX */ - dp->brg_clk_src = EV64260_MPSC_CLK_SRC; - dp->brg_clk_freq = EV64260_MPSC_CLK_FREQ; - } -#endif - - return; -} - static void __init ev64260_setup_arch(void) { - if ( ppc_md.progress ) + if (ppc_md.progress) ppc_md.progress("ev64260_setup_arch: enter", 0); #ifdef CONFIG_BLK_DEV_INITRD @@ -497,41 +369,79 @@ ev64260_setup_arch(void) ROOT_DEV = Root_SDA2; #endif - if ( ppc_md.progress ) + if (ppc_md.progress) ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0); /* Enable L2 and L3 caches (if 745x) */ _set_L2CR(_get_L2CR() | L2CR_L2E); _set_L3CR(_get_L3CR() | L3CR_L3E); - if ( ppc_md.progress ) + if (ppc_md.progress) ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0); ev64260_setup_bridge(); /* set up PCI bridge(s) */ ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */ - if ( ppc_md.progress ) + if (ppc_md.progress) ppc_md.progress("ev64260_setup_arch: bridge init complete", 0); - /* Set OCP values to reflect this board's setup */ - ev64260_fixup_ocp(); - -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE) ev64260_early_serial_map(); #endif - printk(BOARD_VENDOR " " BOARD_MACHINE "\n"); - printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n"); + printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc." + "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE); - if ( ppc_md.progress ) + if (ppc_md.progress) ppc_md.progress("ev64260_setup_arch: exit", 0); return; } +/* Platform device data fixup routines. */ +#if defined(CONFIG_SERIAL_MPSC) +static void __init +ev64260_fixup_mpsc_pdata(struct platform_device *pdev) +{ + struct mpsc_pdata *pdata; + + pdata = (struct mpsc_pdata *)pdev->dev.platform_data; + + pdata->max_idle = 40; + pdata->default_baud = EV64260_DEFAULT_BAUD; + pdata->brg_clk_src = EV64260_MPSC_CLK_SRC; + pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ; + + return; +} + +static int __init +ev64260_platform_notify(struct device *dev) +{ + static struct { + char *bus_id; + void ((*rtn)(struct platform_device *pdev)); + } dev_map[] = { + { MPSC_CTLR_NAME "0", ev64260_fixup_mpsc_pdata }, + { MPSC_CTLR_NAME "1", ev64260_fixup_mpsc_pdata }, + }; + struct platform_device *pdev; + int i; + + if (dev && dev->bus_id) + for (i=0; ibus_id, dev_map[i].bus_id, + BUS_ID_SIZE)) { + + pdev = container_of(dev, + struct platform_device, dev); + dev_map[i].rtn(pdev); + } + + return 0; +} +#endif + static void ev64260_reset_board(void *addr) { @@ -557,28 +467,25 @@ ev64260_reset_board(void *addr) /* unmap any other random cs's that might overlap with bootcs */ mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0); + bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0); + bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0); + bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0); + bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); /* map bootrom back in to gt @ reset defaults */ mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0xff800000, 8*1024*1024, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - /* move gt reg base back to default, setup default pci0 swapping - * config... */ + /* move reg base back to default, setup default pci0 */ mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE, - (1<<24) | MV64x60_INTERNAL_SPACE_DEFAULT_ADDR>>20); + (1<<24) | CONFIG_MV64X60_BASE >> 20); /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped * via BAT or MMU, and MSR IR/DR is ON */ -#if 0 - /* BROKEN... IR/DR is still on !! won't work!! */ - /* Set exception prefix high - to the firmware */ - _nmask_and_or_msr(0, MSR_IP); - - out_8((u_char *)EV64260_BOARD_MODRST_REG, 0x01); -#else /* SRR0 has system reset vector, SRR1 has default MSR value */ /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ /* NOTE: assumes reset vector is at 0xfff00100 */ @@ -588,7 +495,7 @@ ev64260_reset_board(void *addr) "mtspr 27,4\n\t" "rfi\n\t" :: "r" (addr):"r4"); -#endif + return; } @@ -640,7 +547,7 @@ ev64260_calibrate_decr(void) freq = ev64260_get_bus_speed()/4; - printk("time_init: decrementer frequency = %lu.%.6lu MHz\n", + printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", freq/1000000, freq%1000000); tb_ticks_per_jiffy = freq / HZ; @@ -649,142 +556,6 @@ ev64260_calibrate_decr(void) return; } -#if 0 /* XXXX */ -#ifdef CONFIG_USE_PPCBOOT -static void parse_ppcbootinfo(unsigned long r3, - unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - bd_t *bd=NULL; - char *cmdline_start=NULL; - int cmdline_len=0; - - if(r3) { - if((r3 & 0xf0000000) == 0) r3 += KERNELBASE; - if((r3 & 0xf0000000) == KERNELBASE) { - bd=(void *)r3; - - /* hack for ppcboot loaders that report freqs in Mhz */ - if(bd->bi_intfreq<1000000) bd->bi_intfreq*=1000000; - if(bd->bi_busfreq<1000000) bd->bi_busfreq*=1000000; - - memcpy(&ppcboot_bd,bd,sizeof(ppcboot_bd)); - ppcboot_bd_valid=1; - } - } - -#ifdef CONFIG_BLK_DEV_INITRD - if(r4 && r5 && r5>r4) { - if((r4 & 0xf0000000) == 0) r4 += KERNELBASE; - if((r5 & 0xf0000000) == 0) r5 += KERNELBASE; - if((r4 & 0xf0000000) == KERNELBASE) { - initrd_start=r4; - initrd_end=r5; - initrd_below_start_ok = 1; - } - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - if(r6 && r7 && r7>r6) { - if((r6 & 0xf0000000) == 0) r6 += KERNELBASE; - if((r7 & 0xf0000000) == 0) r7 += KERNELBASE; - if((r6 & 0xf0000000) == KERNELBASE) { - cmdline_start=(void *)r6; - cmdline_len=(r7-r6); - strncpy(cmd_line,cmdline_start,cmdline_len); - } - } - - if(ppcboot_bd_valid) { - printk("found bd_t @%p\n", bd); - printk("memstart=%08lx\n", bd->bi_memstart); - printk("memsize=%08lx\n", bd->bi_memsize); - printk("enetaddr=%02x%02x%02x%02x%02x%02x\n", - bd->bi_enetaddr[0], - bd->bi_enetaddr[1], - bd->bi_enetaddr[2], - bd->bi_enetaddr[3], - bd->bi_enetaddr[4], - bd->bi_enetaddr[5] - ); - printk("intfreq=%ld\n", bd->bi_intfreq); - printk("busfreq=%ld\n", bd->bi_busfreq); - printk("baudrate=%ld\n", bd->bi_baudrate); - } - -#ifdef CONFIG_BLK_DEV_INITRD - if(initrd_start) { - printk("found initrd @%lx-%lx\n", initrd_start, initrd_end); - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - if(cmdline_start && cmdline_len) { - printk("found cmdline: '%s'\n", cmd_line); - } -} -#endif /* USE PPC_BOOT */ -#endif - -#if 0 /* XXXX */ -#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) -static int -ev64260_ide_check_region(ide_ioreg_t from, unsigned int extent) -{ - return check_region(from, extent); -} - -static void -ev64260_ide_request_region(ide_ioreg_t from, - unsigned int extent, - const char *name) -{ - request_region(from, extent, name); - return; -} - -static void -ev64260_ide_release_region(ide_ioreg_t from, - unsigned int extent) -{ - release_region(from, extent); - return; -} - -static void __init -ev64260_ide_pci_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, - ide_ioreg_t ctrl_port, int *irq) -{ - struct pci_dev *dev; -#if 1 /* NTL */ - int i; - - //printk("regs %d to %d @ 0x%x\n", IDE_DATA_OFFSET, IDE_STATUS_OFFSET, data_port); - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { - hw->io_ports[i] = data_port; - data_port++; - } - - //printk("ctrl %d @ 0x%x\n", IDE_CONTROL_OFFSET, ctrl_port); - hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; -#endif - - pci_for_each_dev(dev) { - if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) || - ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) { - hw->irq = dev->irq; - - if (irq != NULL) { - *irq = dev->irq; - } - } - } - - return; -} -#endif -#endif - -#if !defined(CONFIG_USE_PPCBOOT) /* * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space. */ @@ -798,7 +569,6 @@ ev64260_set_bat(void) return; } -#endif #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) static void __init @@ -819,18 +589,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, initrd_below_start_ok=0; #endif /* CONFIG_BLK_DEV_INITRD */ - ppcboot_bd_valid=0; - memset(&ppcboot_bd,0,sizeof(ppcboot_bd)); - -#ifdef CONFIG_USE_PPCBOOT - parse_ppcbootinfo(r3, r4, r5, r6, r7); -#else parse_bootinfo(find_bootinfo()); -#endif isa_mem_base = 0; - isa_io_base = 0xa0000000; /* XXXX */ - pci_dram_offset = 0x80000000; /* XXXX */ + isa_io_base = EV64260_PCI0_IO_CPU_BASE; + pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE; loops_per_jiffy = ev64260_get_cpu_speed() / HZ; @@ -839,8 +602,6 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.init_IRQ = gt64260_init_irq; ppc_md.get_irq = gt64260_get_irq; - ppc_md.pcibios_fixup = ev64260_pci_fixups; - ppc_md.restart = ev64260_restart; ppc_md.power_off = ev64260_power_off; ppc_md.halt = ev64260_halt; @@ -852,21 +613,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.time_init = todc_time_init; ppc_md.set_rtc_time = todc_set_rtc_time; ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; ppc_md.nvram_write_val = todc_direct_write_val; - ppc_md.calibrate_decr = ev64260_calibrate_decr; -#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) - ppc_ide_md.ide_init_hwif = ev64260_ide_pci_init_hwif_ports; -#endif - bh.p_base = CONFIG_MV64X60_NEW_BASE; -#if !defined(CONFIG_USE_PPCBOOT) ev64260_set_bat(); -#endif #ifdef CONFIG_SERIAL_8250 #if defined(CONFIG_SERIAL_TEXT_DEBUG) @@ -880,13 +633,18 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, #elif defined(CONFIG_SERIAL_MPSC_CONSOLE) #ifdef CONFIG_SERIAL_TEXT_DEBUG ppc_md.setup_io_mappings = ev64260_map_io; - ppc_md.progress = gt64260_mpsc_progress; + ppc_md.progress = mv64x60_mpsc_progress; + mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); #endif /* CONFIG_SERIAL_TEXT_DEBUG */ #ifdef CONFIG_KGDB ppc_md.setup_io_mappings = ev64260_map_io; ppc_md.early_serial_map = ev64260_early_serial_map; #endif /* CONFIG_KGDB */ +#endif + +#if defined(CONFIG_SERIAL_MPSC) + platform_notify = ev64260_platform_notify; #endif return;