X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fhdpu.c;fp=arch%2Fppc%2Fplatforms%2Fhdpu.c;h=50039a204c2495f739b9e4637ba553a0f3a5f9dd;hb=64ba3f394c830ec48a1c31b53dcae312c56f1604;hp=e0f112a1fd0b4926675cfc1d4eae7421e341dba4;hpb=be1e6109ac94a859551f8e1774eb9a8469fe055c;p=linux-2.6.git

diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c
index e0f112a1f..50039a204 100644
--- a/arch/ppc/platforms/hdpu.c
+++ b/arch/ppc/platforms/hdpu.c
@@ -1,4 +1,7 @@
+
 /*
+ * arch/ppc/platforms/hdpu_setup.c
+ *
  * Board setup routines for the Sky Computers HDPU Compute Blade.
  *
  * Written by Brian Waite <waite@skycomputers.com>
@@ -12,6 +15,7 @@
  * option) any later version.
  */
 
+#include <linux/config.h>
 
 #include <linux/pci.h>
 #include <linux/delay.h>
@@ -315,10 +319,11 @@ static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
 	struct mv643xx_eth_platform_data *eth_pd;
 	eth_pd = pd->dev.platform_data;
 
+	eth_pd->port_serial_control =
+	    mv64x60_read(&bh, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd->id) & ~1);
+
 	eth_pd->force_phy_addr = 1;
 	eth_pd->phy_addr = pd->id;
-	eth_pd->speed = SPEED_100;
-	eth_pd->duplex = DUPLEX_FULL;
 	eth_pd->tx_queue_size = 400;
 	eth_pd->rx_queue_size = 800;
 }
@@ -349,7 +354,7 @@ static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
 }
 #endif
 
-static int hdpu_platform_notify(struct device *dev)
+static int __init hdpu_platform_notify(struct device *dev)
 {
 	static struct {
 		char *bus_id;
@@ -837,7 +842,7 @@ static void smp_hdpu_setup_cpu(int cpu_nr)
 		mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
 		mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
 		request_irq(60, hdpu_smp_cpu0_int_handler,
-			    IRQF_DISABLED, hdpu_smp0, 0);
+			    SA_INTERRUPT, hdpu_smp0, 0);
 	}
 
 	if (cpu_nr == 1) {
@@ -857,7 +862,7 @@ static void smp_hdpu_setup_cpu(int cpu_nr)
 		mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
 		mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
 		request_irq(28, hdpu_smp_cpu1_int_handler,
-			    IRQF_DISABLED, hdpu_smp1, 0);
+			    SA_INTERRUPT, hdpu_smp1, 0);
 	}
 
 }