X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fmcpn765.h;h=4d35ecad097b0e9dbb1cf804f52294347ed7ed2b;hb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;hp=87233831763e0aa3e69ac66d589cb77a49d51e1b;hpb=a2c21200f1c81b08cb55e417b68150bba439b646;p=linux-2.6.git

diff --git a/arch/ppc/platforms/mcpn765.h b/arch/ppc/platforms/mcpn765.h
index 872338317..4d35ecad0 100644
--- a/arch/ppc/platforms/mcpn765.h
+++ b/arch/ppc/platforms/mcpn765.h
@@ -6,7 +6,7 @@
  * Author: Mark A. Greer
  *         mgreer@mvista.com
  *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
@@ -25,6 +25,7 @@
 
 #ifndef __PPC_PLATFORMS_MCPN765_H
 #define __PPC_PLATFORMS_MCPN765_H
+#include <linux/config.h>
 
 /* PCI Memory space mapping info */
 #define	MCPN765_PCI_MEM_SIZE		0x40000000U
@@ -65,14 +66,57 @@
 #define	MCPN765_BOARD_EXT_FEATURE_REG	0xfef880f0U
 #define	MCPN765_BOARD_LAST_RESET_REG	0xfef880f8U
 
-/* UART base addresses are defined in <asm-ppc/platforms/mcpn765_serial.h> */
+/* Defines for UART */
+
+/* Define the UART base addresses */
+#define	MCPN765_SERIAL_1		0xfef88000
+#define	MCPN765_SERIAL_2		0xfef88200
+#define	MCPN765_SERIAL_3		0xfef88400
+#define	MCPN765_SERIAL_4		0xfef88600
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define RS_TABLE_SIZE  64
+#else
+#define RS_TABLE_SIZE  4
+#endif
+
+/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
+#define BASE_BAUD	( 1843200 / 16 )
+#define UART_CLK	1843200
+
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
+#endif
+
+/* All UART IRQ's are wire-OR'd to IRQ 17 */
+#define STD_SERIAL_PORT_DFNS \
+        { 0, BASE_BAUD, MCPN765_SERIAL_1, 17, STD_COM_FLAGS, /* ttyS0 */\
+		iomem_base: (u8 *)MCPN765_SERIAL_1,			\
+		iomem_reg_shift: 4,					\
+		io_type: SERIAL_IO_MEM },				\
+        { 0, BASE_BAUD, MCPN765_SERIAL_2, 17, STD_COM_FLAGS, /* ttyS1 */\
+		iomem_base: (u8 *)MCPN765_SERIAL_2,			\
+		iomem_reg_shift: 4,					\
+		io_type: SERIAL_IO_MEM },				\
+        { 0, BASE_BAUD, MCPN765_SERIAL_3, 17, STD_COM_FLAGS, /* ttyS2 */\
+		iomem_base: (u8 *)MCPN765_SERIAL_3,			\
+		iomem_reg_shift: 4,					\
+		io_type: SERIAL_IO_MEM },				\
+        { 0, BASE_BAUD, MCPN765_SERIAL_4, 17, STD_COM_FLAGS, /* ttyS3 */\
+		iomem_base: (u8 *)MCPN765_SERIAL_4,			\
+		iomem_reg_shift: 4,					\
+		io_type: SERIAL_IO_MEM },
+
+#define SERIAL_PORT_DFNS \
+        STD_SERIAL_PORT_DFNS
 
 /* Define the NVRAM/RTC address strobe & data registers */
 #define MCPN765_PHYS_NVRAM_AS0          0xfef880c8U
 #define MCPN765_PHYS_NVRAM_AS1          0xfef880d0U
 #define MCPN765_PHYS_NVRAM_DATA         0xfef880d8U
 
-
 extern void mcpn765_find_bridges(void);
 
 #endif /* __PPC_PLATFORMS_MCPN765_H */