X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fpmac_pci.c;h=f6ff5192406115765036aaf0d386431acbb23073;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=9dcc4e2e539958acb4276b290fe12e5dc7364936;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git diff --git a/arch/ppc/platforms/pmac_pci.c b/arch/ppc/platforms/pmac_pci.c index 9dcc4e2e5..f6ff51924 100644 --- a/arch/ppc/platforms/pmac_pci.c +++ b/arch/ppc/platforms/pmac_pci.c @@ -50,8 +50,9 @@ static struct pci_controller *u3_agp; #endif /* CONFIG_POWER4 */ extern u8 pci_cache_line_size; +extern int pcibios_assign_bus_offset; -struct pci_dev *k2_skiplist[2]; +struct device_node *k2_skiplist[2]; /* * Magic constants for enabling cache coherency in the bandit/PSX bridge. @@ -141,14 +142,14 @@ fixup_bus_range(struct device_node *bridge) |(((unsigned long)(off)) & 0xFCUL) \ |1UL) -static unsigned int __pmac +static void volatile __iomem * __pmac macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) { unsigned int caddr; if (bus == hose->first_busno) { if (dev_fn < (11 << 3)) - return 0; + return NULL; caddr = MACRISC_CFA0(dev_fn, offset); } else caddr = MACRISC_CFA1(bus, dev_fn, offset); @@ -159,7 +160,7 @@ macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) } while (in_le32(hose->cfg_addr) != caddr); offset &= has_uninorth ? 0x07 : 0x03; - return (unsigned int)(hose->cfg_data) + (unsigned int)offset; + return hose->cfg_data + offset; } static int __pmac @@ -167,7 +168,7 @@ macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = bus->sysdata; - unsigned int addr; + void volatile __iomem *addr; addr = macrisc_cfg_access(hose, bus->number, devfn, offset); if (!addr) @@ -178,13 +179,13 @@ macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, */ switch (len) { case 1: - *val = in_8((u8 *)addr); + *val = in_8(addr); break; case 2: - *val = in_le16((u16 *)addr); + *val = in_le16(addr); break; default: - *val = in_le32((u32 *)addr); + *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -195,7 +196,7 @@ macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose = bus->sysdata; - unsigned int addr; + void volatile __iomem *addr; addr = macrisc_cfg_access(hose, bus->number, devfn, offset); if (!addr) @@ -206,16 +207,16 @@ macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, */ switch (len) { case 1: - out_8((u8 *)addr, val); - (void) in_8((u8 *)addr); + out_8(addr, val); + (void) in_8(addr); break; case 2: - out_le16((u16 *)addr, val); - (void) in_le16((u16 *)addr); + out_le16(addr, val); + (void) in_le16(addr); break; default: - out_le32((u32 *)addr, val); - (void) in_le32((u32 *)addr); + out_le32(addr, val); + (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -294,7 +295,7 @@ static struct pci_ops chaos_pci_ops = + (((unsigned long)bus) << 16) \ + 0x01000000UL) -static unsigned long __pmac +static void volatile __iomem * __pmac u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) { if (bus == hose->first_busno) { @@ -302,9 +303,9 @@ u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 || PCI_SLOT(devfn) < 1) return 0; - return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); + return hose->cfg_data + U3_HT_CFA0(devfn, offset); } else - return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); + return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); } static int __pmac @@ -312,16 +313,19 @@ u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = bus->sysdata; - unsigned int addr; + void volatile __iomem *addr; int i; + struct device_node *np = pci_busdev_to_OF_node(bus, devfn); + if (np == NULL) + return PCIBIOS_DEVICE_NOT_FOUND; + /* * When a device in K2 is powered down, we die on config * cycle accesses. Fix that here. */ for (i=0; i<2; i++) - if (k2_skiplist[i] && k2_skiplist[i]->bus == bus && - k2_skiplist[i]->devfn == devfn) { + if (k2_skiplist[i] == np) { switch (len) { case 1: *val = 0xff; break; @@ -342,13 +346,13 @@ u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, */ switch (len) { case 1: - *val = in_8((u8 *)addr); + *val = in_8(addr); break; case 2: - *val = in_le16((u16 *)addr); + *val = in_le16(addr); break; default: - *val = in_le32((u32 *)addr); + *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -359,16 +363,18 @@ u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose = bus->sysdata; - unsigned int addr; + void volatile __iomem *addr; int i; + struct device_node *np = pci_busdev_to_OF_node(bus, devfn); + if (np == NULL) + return PCIBIOS_DEVICE_NOT_FOUND; /* * When a device in K2 is powered down, we die on config * cycle accesses. Fix that here. */ for (i=0; i<2; i++) - if (k2_skiplist[i] && k2_skiplist[i]->bus == bus && - k2_skiplist[i]->devfn == devfn) + if (k2_skiplist[i] == np) return PCIBIOS_SUCCESSFUL; addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); @@ -380,16 +386,16 @@ u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, */ switch (len) { case 1: - out_8((u8 *)addr, val); - (void) in_8((u8 *)addr); + out_8(addr, val); + (void) in_8(addr); break; case 2: - out_le16((u16 *)addr, val); - (void) in_le16((u16 *)addr); + out_le16(addr, val); + (void) in_le16(addr); break; default: - out_le32((u32 *)addr, val); - (void) in_le32((u32 *)addr); + out_le32(addr, val); + (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -416,7 +422,7 @@ init_bandit(struct pci_controller *bp) /* read the word at offset 0 in config space for device 11 */ out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); udelay(2); - vendev = in_le32((volatile unsigned int *)bp->cfg_data); + vendev = in_le32(bp->cfg_data); if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + PCI_VENDOR_ID_APPLE) { /* read the revision id */ @@ -435,12 +441,12 @@ init_bandit(struct pci_controller *bp) /* read the word at offset 0x50 */ out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); udelay(2); - magic = in_le32((volatile unsigned int *)bp->cfg_data); + magic = in_le32(bp->cfg_data); if ((magic & BANDIT_COHERENT) != 0) return; magic |= BANDIT_COHERENT; udelay(2); - out_le32((volatile unsigned int *)bp->cfg_data, magic); + out_le32(bp->cfg_data, magic); printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); } @@ -565,6 +571,14 @@ pmac_find_bridges(void) init_p2pbridge(); fixup_nec_usb2(); + + /* We are still having some issues with the Xserve G4, enabling + * some offset between bus number and domains for now when we + * assign all busses should help for now + */ + if (pci_assign_all_busses) + pcibios_assign_bus_offset = 0x10; + #ifdef CONFIG_POWER4 /* There is something wrong with DMA on U3/HT. I haven't figured out * the details yet, but if I set the cache line size to 128 bytes like @@ -606,12 +620,12 @@ static inline void grackle_set_stg(struct pci_controller* bp, int enable) unsigned int val; out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); - val = in_le32((volatile unsigned int *)bp->cfg_data); + val = in_le32(bp->cfg_data); val = enable? (val | GRACKLE_PICR1_STG) : (val & ~GRACKLE_PICR1_STG); out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); - out_le32((volatile unsigned int *)bp->cfg_data, val); - (void)in_le32((volatile unsigned int *)bp->cfg_data); + out_le32(bp->cfg_data, val); + (void)in_le32(bp->cfg_data); } static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) @@ -619,12 +633,12 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) unsigned int val; out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); - val = in_le32((volatile unsigned int *)bp->cfg_data); + val = in_le32(bp->cfg_data); val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) : (val & ~GRACKLE_PICR1_LOOPSNOOP); out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); - out_le32((volatile unsigned int *)bp->cfg_data, val); - (void)in_le32((volatile unsigned int *)bp->cfg_data); + out_le32(bp->cfg_data, val); + (void)in_le32(bp->cfg_data); } static int __init @@ -643,10 +657,8 @@ static void __init setup_bandit(struct pci_controller* hose, struct reg_property* addr) { hose->ops = ¯isc_pci_ops; - hose->cfg_addr = (volatile unsigned int *) - ioremap(addr->address + 0x800000, 0x1000); - hose->cfg_data = (volatile unsigned char *) - ioremap(addr->address + 0xc00000, 0x1000); + hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); + hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); init_bandit(hose); } @@ -655,10 +667,8 @@ setup_chaos(struct pci_controller* hose, struct reg_property* addr) { /* assume a `chaos' bridge */ hose->ops = &chaos_pci_ops; - hose->cfg_addr = (volatile unsigned int *) - ioremap(addr->address + 0x800000, 0x1000); - hose->cfg_data = (volatile unsigned char *) - ioremap(addr->address + 0xc00000, 0x1000); + hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); + hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); } #ifdef CONFIG_POWER4 @@ -697,7 +707,7 @@ setup_u3_ht(struct pci_controller* hose, struct reg_property *addr) * the reg address cell, we shall fix that by killing struct * reg_property and using some accessor functions instead */ - hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); + hose->cfg_data = ioremap(0xf2000000, 0x02000000); /* * /ht node doesn't expose a "ranges" property, so we "remove" regions that @@ -707,7 +717,7 @@ setup_u3_ht(struct pci_controller* hose, struct reg_property *addr) * properties or figuring out the U3 address space decoding logic and * then read its configuration register (if any). */ - hose->io_base_phys = 0xf4000000 + 0x00400000; + hose->io_base_phys = 0xf4000000; hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000); isa_io_base = (unsigned long) hose->io_base_virt; hose->io_resource.name = np->full_name; @@ -873,7 +883,7 @@ pcibios_fixup_OF_interrupts(void) * should find the device node and apply the interrupt * obtained from the OF device-tree */ - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + for_each_pci_dev(dev) { struct device_node *node; node = pci_device_to_OF_node(dev); /* this is the node, see if it has interrupts */ @@ -903,8 +913,12 @@ pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) * (iBook second controller) */ if (dev->vendor == PCI_VENDOR_ID_APPLE - && dev->device == PCI_DEVICE_ID_APPLE_KL_USB && !node) + && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) + && !node) { + printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", + pci_name(dev)); return -EINVAL; + } if (!node) return 0; @@ -973,7 +987,7 @@ pmac_pcibios_after_init(void) * * -- BenH */ - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + for_each_pci_dev(dev) { if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) pci_enable_device(dev); } @@ -1034,6 +1048,8 @@ void pmac_pci_fixup_cardbus(struct pci_dev* dev) } } +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); + void pmac_pci_fixup_pciata(struct pci_dev* dev) { u8 progif = 0; @@ -1074,6 +1090,8 @@ void pmac_pci_fixup_pciata(struct pci_dev* dev) printk(KERN_ERR "Rewrite of PROGIF failed !\n"); } } +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); + /* * Disable second function on K2-SATA, it's broken @@ -1104,3 +1122,4 @@ void __pmac pmac_pci_fixup_k2_sata(struct pci_dev* dev) } } } +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, pmac_pci_fixup_k2_sata);