X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fsandpoint.c;h=a76002af686ff9416f35a1d7964fb7bf5b9b2d8f;hb=16c70f8c1b54b61c3b951b6fb220df250fe09b32;hp=b07f416cc0d40c3e3ba7eb10f3b424dd7dde0a1f;hpb=6a77f38946aaee1cd85eeec6cf4229b204c15071;p=linux-2.6.git diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c index b07f416cc..a76002af6 100644 --- a/arch/ppc/platforms/sandpoint.c +++ b/arch/ppc/platforms/sandpoint.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sandpoint_setup.c - * * Board setup routines for the Motorola SPS Sandpoint Test Platform. * * Author: Mark A. Greer @@ -62,7 +60,6 @@ * found, we can hopefully stop hardcoding 32MB of RAM. */ -#include #include #include #include @@ -74,13 +71,13 @@ #include #include #include -#include #include #include #include #include #include /* for linux/serial_core.h */ #include +#include #include #include @@ -99,6 +96,7 @@ #include #include #include +#include #include "sandpoint.h" @@ -202,13 +200,6 @@ sandpoint_setup_winbond_83553(struct pci_controller *hose) 0x48, /* ISA-to-PCI Addr Decoder Control */ 0xf0); - /* Enable RTC and Keyboard address locations. */ - early_write_config_byte(hose, - 0, - devfn, - 0x4d, /* Chip Select Control Register */ - 0x00); - /* Enable Port 92. */ early_write_config_byte(hose, 0, @@ -312,6 +303,28 @@ sandpoint_setup_arch(void) /* Lookup PCI host bridges */ sandpoint_find_bridges(); + if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0) + { + bd_t *bp = (bd_t *)__res; + struct plat_serial8250_port *pdata; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0); + if (pdata) + { + pdata[0].uartclk = bp->bi_busfreq; + } + +#ifdef CONFIG_SANDPOINT_ENABLE_UART1 + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1); + if (pdata) + { + pdata[0].uartclk = bp->bi_busfreq; + } +#else + ppc_sys_device_remove(MPC10X_UART1); +#endif + } + printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n"); @@ -319,10 +332,10 @@ sandpoint_setup_arch(void) * We will do this now with good known values. Future versions * of DINK32 are supposed to get this correct. */ - if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450) + if (cpu_has_feature(CPU_FTR_SPEC7450)) /* 745x is different. We only want to pass along enable. */ _set_L2CR(L2CR_L2E); - else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR) + else if (cpu_has_feature(CPU_FTR_L2CR)) /* All modules have 1MB of L2. We also assume that an * L2 divisor of 3 will work. */ @@ -330,7 +343,7 @@ sandpoint_setup_arch(void) | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); #if 0 /* Untested right now. */ - if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) { + if (cpu_has_feature(CPU_FTR_L3CR)) { /* Magic value. */ _set_L3CR(0x8f032000); } @@ -477,28 +490,11 @@ sandpoint_init_IRQ(void) openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade", i8259_irq); - /* - * openpic_init() has set up irq_desc[16-31] to be openpic - * interrupts. We need to set irq_desc[0-15] to be i8259 - * interrupts. - */ - for(i=0; i < NUM_8259_INTERRUPTS; i++) - irq_desc[i].handler = &i8259_pic; - /* * The EPIC allows for a read in the range of 0xFEF00000 -> * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction. */ - i8259_init(0xfef00000); -} - -static u32 -sandpoint_irq_canonicalize(u32 irq) -{ - if (irq == 2) - return 9; - else - return irq; + i8259_init(0xfef00000, 0); } static unsigned long __init @@ -711,10 +707,10 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ISA_DMA_THRESHOLD = 0x00ffffff; DMA_MODE_READ = 0x44; DMA_MODE_WRITE = 0x48; + ppc_do_canonicalize_irqs = 1; ppc_md.setup_arch = sandpoint_setup_arch; ppc_md.show_cpuinfo = sandpoint_show_cpuinfo; - ppc_md.irq_canonicalize = sandpoint_irq_canonicalize; ppc_md.init_IRQ = sandpoint_init_IRQ; ppc_md.get_irq = openpic_get_irq;