X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fsyslib%2Fmpc10x_common.c;h=2fc7c4150a18890f94c6fc851e0ab6f66a18419b;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=fd93adfd464c6d51e437e9ff4fb32e57a30d0d05;hpb=cee37fe97739d85991964371c1f3a745c00dd236;p=linux-2.6.git diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c index fd93adfd4..2fc7c4150 100644 --- a/arch/ppc/syslib/mpc10x_common.c +++ b/arch/ppc/syslib/mpc10x_common.c @@ -1,6 +1,4 @@ /* - * arch/ppc/syslib/mpc10x_common.c - * * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, * Mem ctlr, EPIC, etc. * @@ -21,6 +19,9 @@ #include #include #include +#include +#include +#include #include #include @@ -30,16 +31,7 @@ #include #include #include -#include - -/* The OCP structure is fixed by code below, before OCP initialises. - paddr depends on where the board places the EUMB. - - fixed in mpc10x_bridge_init(). - irq depends on two things: - > does the board use the EPIC at all? (PCORE does not). - > is the EPIC in serial or parallel mode? - - fixed in mpc10x_set_openpic(). -*/ +#include #ifdef CONFIG_MPC10X_OPENPIC #ifdef CONFIG_EPIC_SERIAL_MODE @@ -50,37 +42,172 @@ #define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS) #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS) #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS) +#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS) +#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS) #else -#define MPC10X_I2C_IRQ OCP_IRQ_NA -#define MPC10X_DMA0_IRQ OCP_IRQ_NA -#define MPC10X_DMA1_IRQ OCP_IRQ_NA +#define MPC10X_I2C_IRQ -1 +#define MPC10X_DMA0_IRQ -1 +#define MPC10X_DMA1_IRQ -1 +#define MPC10X_UART0_IRQ -1 +#define MPC10X_UART1_IRQ -1 #endif - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_INVALID - } +static struct fsl_i2c_platform_data mpc10x_i2c_pdata = { + .device_flags = 0, }; -static struct ocp_fs_i2c_data mpc10x_i2c_data = { - .flags = 0 +static struct plat_serial8250_port serial_plat_uart0[] = { + [0] = { + .mapbase = 0x4500, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, + { }, }; -static struct ocp_def mpc10x_i2c_ocp = { - .vendor = OCP_VENDOR_MOTOROLA, - .function = OCP_FUNC_IIC, - .index = 0, - .additions = &mpc10x_i2c_data +static struct plat_serial8250_port serial_plat_uart1[] = { + [0] = { + .mapbase = 0x4600, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, + { }, +}; + +struct platform_device ppc_sys_platform_devices[] = { + [MPC10X_IIC1] = { + .name = "fsl-i2c", + .id = 1, + .dev.platform_data = &mpc10x_i2c_pdata, + .num_resources = 2, + .resource = (struct resource[]) { + { + .start = MPC10X_EUMB_I2C_OFFSET, + .end = MPC10X_EUMB_I2C_OFFSET + + MPC10X_EUMB_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ + }, + }, + }, + [MPC10X_DMA0] = { + .name = "fsl-dma", + .id = 0, + .num_resources = 2, + .resource = (struct resource[]) { + { + .start = MPC10X_EUMB_DMA_OFFSET + 0x10, + .end = MPC10X_EUMB_DMA_OFFSET + 0x1f, + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC10X_DMA1] = { + .name = "fsl-dma", + .id = 1, + .num_resources = 2, + .resource = (struct resource[]) { + { + .start = MPC10X_EUMB_DMA_OFFSET + 0x20, + .end = MPC10X_EUMB_DMA_OFFSET + 0x2f, + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC10X_DMA1] = { + .name = "fsl-dma", + .id = 1, + .num_resources = 2, + .resource = (struct resource[]) { + { + .start = MPC10X_EUMB_DMA_OFFSET + 0x20, + .end = MPC10X_EUMB_DMA_OFFSET + 0x2f, + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC10X_UART0] = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = serial_plat_uart0, + }, + [MPC10X_UART1] = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev.platform_data = serial_plat_uart1, + }, + }; -static struct ocp_def mpc10x_dma_ocp[2] = { -{ .vendor = OCP_VENDOR_MOTOROLA, - .function = OCP_FUNC_DMA, - .index = 0 }, -{ .vendor = OCP_VENDOR_MOTOROLA, - .function = OCP_FUNC_DMA, - .index = 1 } +/* We use the PCI ID to match on */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + .ppc_sys_name = "8245", + .mask = 0xFFFFFFFF, + .value = MPC10X_BRIDGE_8245, + .num_devices = 5, + .device_list = (enum ppc_sys_devices[]) + { + MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1, + }, + }, + { + .ppc_sys_name = "8240", + .mask = 0xFFFFFFFF, + .value = MPC10X_BRIDGE_8240, + .num_devices = 3, + .device_list = (enum ppc_sys_devices[]) + { + MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, + }, + }, + { + .ppc_sys_name = "107", + .mask = 0xFFFFFFFF, + .value = MPC10X_BRIDGE_107, + .num_devices = 3, + .device_list = (enum ppc_sys_devices[]) + { + MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, + }, + }, + { /* default match */ + .ppc_sys_name = "", + .mask = 0x00000000, + .value = 0x00000000, + }, }; +/* + * mach_mpc10x_fixup: This function enables DUART mode if it detects + * if it detects two UARTS in the platform device entries. + */ +static int __init mach_mpc10x_fixup(struct platform_device *pdev) +{ + if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1) + writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1, + serial_plat_uart1[0].membase + 0x11); + return 0; +} + +static int __init mach_mpc10x_init(void) +{ + ppc_sys_device_fixup = mach_mpc10x_fixup; + return 0; +} +postcore_initcall(mach_mpc10x_init); + /* Set resources to match bridge memory map */ void __init mpc10x_bridge_set_resources(int map, struct pci_controller *hose) @@ -120,6 +247,7 @@ mpc10x_bridge_set_resources(int map, struct pci_controller *hose) ppc_md.progress("mpc10x:exit1", 0x100); } } + /* * Do some initialization and put the EUMB registers at the specified address * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set). @@ -132,7 +260,7 @@ mpc10x_bridge_init(struct pci_controller *hose, uint new_map, uint phys_eumb_base) { - int host_bridge, picr1, picr1_bit; + int host_bridge, picr1, picr1_bit, i; ulong pci_config_addr, pci_config_data; u_char pir, byte; @@ -273,7 +401,7 @@ mpc10x_bridge_init(struct pci_controller *hose, printk("Host bridge in Agent mode\n"); /* Read or Set LMBAR & PCSRBAR? */ } - + /* Set base addr of the 8240/107 EUMB. */ early_write_config_dword(hose, 0, @@ -287,17 +415,6 @@ mpc10x_bridge_init(struct pci_controller *hose, ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET, MPC10X_EUMB_EPIC_SIZE); #endif - mpc10x_i2c_ocp.paddr = phys_eumb_base + MPC10X_EUMB_I2C_OFFSET; - mpc10x_i2c_ocp.irq = MPC10X_I2C_IRQ; - ocp_add_one_device(&mpc10x_i2c_ocp); - mpc10x_dma_ocp[0].paddr = phys_eumb_base + - MPC10X_EUMB_DMA_OFFSET + 0x100; - mpc10x_dma_ocp[0].irq = MPC10X_DMA0_IRQ; - ocp_add_one_device(&mpc10x_dma_ocp[0]); - mpc10x_dma_ocp[1].paddr = phys_eumb_base + - MPC10X_EUMB_DMA_OFFSET + 0x200; - mpc10x_dma_ocp[1].irq = MPC10X_DMA1_IRQ; - ocp_add_one_device(&mpc10x_dma_ocp[1]); } #ifdef CONFIG_MPC10X_STORE_GATHERING @@ -306,6 +423,31 @@ mpc10x_bridge_init(struct pci_controller *hose, mpc10x_disable_store_gathering(hose); #endif + /* setup platform devices for MPC10x bridges */ + identify_ppc_sys_by_id (host_bridge); + + for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) { + unsigned int dev_id = cur_ppc_sys_spec->device_list[i]; + ppc_sys_fixup_mem_resource(&ppc_sys_platform_devices[dev_id], + phys_eumb_base); + } + + /* IRQ's are determined at runtime */ + ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ; + ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ; + ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ; + ppc_sys_platform_devices[MPC10X_DMA0].resource[1].end = MPC10X_DMA0_IRQ; + ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ; + ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ; + + serial_plat_uart0[0].mapbase += phys_eumb_base; + serial_plat_uart0[0].irq = MPC10X_UART0_IRQ; + serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100); + + serial_plat_uart1[0].mapbase += phys_eumb_base; + serial_plat_uart1[0].irq = MPC10X_UART1_IRQ; + serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100); + /* * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative * PCI reads may return stale data so turn off. @@ -330,7 +472,7 @@ mpc10x_bridge_init(struct pci_controller *hose, * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd. */ if (host_bridge == MPC10X_BRIDGE_8245) { - ulong picr2; + u32 picr2; early_read_config_dword(hose, 0, PCI_DEVFN(0,0), MPC10X_CFG_PICR2_REG, &picr2); @@ -504,6 +646,8 @@ void __init mpc10x_set_openpic(void) openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020); /* Skip reserved space and map Message Unit Interrupt (I2O) */ openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0); + /* Skip reserved space and map Serial Interupts */ + openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120); openpic_init(NUM_8259_INTERRUPTS); }