X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fsyslib%2Fppc4xx_setup.c;h=debe14c083a12834b76477b03b2f9c6ace7cae32;hb=refs%2Fheads%2Fvserver;hp=f7458822f7b6bfe3dcdf97e1ee637d5640523400;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/ppc/syslib/ppc4xx_setup.c b/arch/ppc/syslib/ppc4xx_setup.c index f7458822f..debe14c08 100644 --- a/arch/ppc/syslib/ppc4xx_setup.c +++ b/arch/ppc/syslib/ppc4xx_setup.c @@ -13,12 +13,10 @@ * */ -#include #include #include #include #include -#include #include #include #include @@ -42,29 +40,31 @@ #include #include +#include + /* Function Prototypes */ extern void abort(void); extern void ppc4xx_find_bridges(void); -extern void ppc4xx_wdt_heartbeat(void); -extern int wdt_enable; -extern unsigned long wdt_period; - /* Global Variables */ bd_t __res; void __init ppc4xx_setup_arch(void) { - /* Setup PCI host bridges */ +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + mtspr(SPRN_DBCR0, (DBCR0_IDM)); + mtspr(SPRN_DBSR, 0xffffffff); +#endif + /* Setup PCI host bridges */ #ifdef CONFIG_PCI ppc4xx_find_bridges(); #endif - -#if defined(CONFIG_FB) - conswitchp = &dummy_con; -#endif } /* @@ -127,12 +127,7 @@ ppc4xx_map_io(void) void __init ppc4xx_init_IRQ(void) { - int i; - ppc4xx_pic_init(); - - for (i = 0; i < NR_IRQS; i++) - irq_desc[i].handler = ppc4xx_pic; } static void @@ -170,7 +165,7 @@ ppc4xx_calibrate_decr(void) unsigned int freq; bd_t *bip = &__res; -#if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE) +#if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE) /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */ mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); #endif @@ -193,34 +188,6 @@ ppc4xx_calibrate_decr(void) /* Set the PIT reload value and just let it run. */ mtspr(SPRN_PIT, tb_ticks_per_jiffy); } -#ifdef CONFIG_SERIAL_TEXT_DEBUG - -/* We assume that the UART has already been initialized by the - firmware or the boot loader */ -static void -serial_putc(u8 * com_port, unsigned char c) -{ - while ((readb(com_port + (UART_LSR)) & UART_LSR_THRE) == 0) ; - writeb(c, com_port); -} - -static void -ppc4xx_progress(char *s, unsigned short hex) -{ - char c; -#ifdef SERIAL_DEBUG_IO_BASE - u8 *com_port = (u8 *) SERIAL_DEBUG_IO_BASE; - - while ((c = *s++) != '\0') { - serial_putc(com_port, c); - } - serial_putc(com_port, '\r'); - serial_putc(com_port, '\n'); -#else - printk("%s\r\n"); -#endif -} -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ /* * IDE stuff. @@ -284,22 +251,6 @@ ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, *(char *) (r7 + KERNELBASE) = 0; strcpy(cmd_line, (char *) (r6 + KERNELBASE)); } -#if defined(CONFIG_PPC405_WDT) -/* Look for wdt= option on command line */ - if (strstr(cmd_line, "wdt=")) { - int valid_wdt = 0; - char *p, *q; - for (q = cmd_line; (p = strstr(q, "wdt=")) != 0;) { - q = p + 4; - if (p > cmd_line && p[-1] != ' ') - continue; - wdt_period = simple_strtoul(q, &q, 0); - valid_wdt = 1; - ++q; - } - wdt_enable = valid_wdt; - } -#endif /* Initialize machine-dependent vectors */ @@ -314,23 +265,30 @@ ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.calibrate_decr = ppc4xx_calibrate_decr; -#ifdef CONFIG_PPC405_WDT - ppc_md.heartbeat = ppc4xx_wdt_heartbeat; -#endif - ppc_md.heartbeat_count = 0; - ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory; ppc_md.setup_io_mappings = ppc4xx_map_io; #ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = ppc4xx_progress; + ppc_md.progress = gen550_progress; #endif -/* -** m8xx_setup.c, prep_setup.c use -** defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) -*/ #if defined(CONFIG_PCI) && defined(CONFIG_IDE) ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports; #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */ } + +/* Called from machine_check_exception */ +void platform_machine_check(struct pt_regs *regs) +{ +#if defined(DCRN_PLB0_BEAR) + printk("PLB0: BEAR= 0x%08x ACR= 0x%08x BESR= 0x%08x\n", + mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR), + mfdcr(DCRN_PLB0_BESR)); +#endif +#if defined(DCRN_POB0_BEAR) + printk("PLB0 to OPB: BEAR= 0x%08x BESR0= 0x%08x BESR1= 0x%08x\n", + mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0), + mfdcr(DCRN_POB0_BESR1)); +#endif + +}