X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fsyslib%2Fppc8260_pic.c;fp=arch%2Fppc%2Fsyslib%2Fcpm2_pic.c;h=7faeb90bef7a19aae31b21c87110fd2ba9ac6072;hb=f9296eb00ed30209424102d3c920e69617eea853;hp=43eac4135feffb9c615d2912b3d4f9f2d7113943;hpb=a91482bdcc2e0f6035702e46f1b99043a0893346;p=linux-2.6.git

diff --git a/arch/ppc/syslib/cpm2_pic.c b/arch/ppc/syslib/ppc8260_pic.c
similarity index 74%
rename from arch/ppc/syslib/cpm2_pic.c
rename to arch/ppc/syslib/ppc8260_pic.c
index 43eac4135..7faeb90be 100644
--- a/arch/ppc/syslib/cpm2_pic.c
+++ b/arch/ppc/syslib/ppc8260_pic.c
@@ -3,11 +3,11 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <asm/irq.h>
-#include <asm/immap_cpm2.h>
+#include <asm/immap_8260.h>
 #include <asm/mpc8260.h>
-#include "cpm2_pic.h"
+#include "ppc8260_pic.h"
 
-/* The CPM2 internal interrupt controller.  It is usually
+/* The 8260 internal interrupt controller.  It is usually
  * the only interrupt controller.
  * There are two 32-bit registers (high/low) for up to 64
  * possible interrupts.
@@ -40,7 +40,7 @@ static	u_char	irq_to_siubit[] = {
 	 7,  6,  5,  4,  3,  2,  1,  0
 };
 
-static void cpm2_mask_irq(unsigned int irq_nr)
+static void m8260_mask_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -48,12 +48,12 @@ static void cpm2_mask_irq(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(cpm2_immr->im_intctl.ic_simrh);
+	simr = &(immr->im_intctl.ic_simrh);
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 }
 
-static void cpm2_unmask_irq(unsigned int irq_nr)
+static void m8260_unmask_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -61,12 +61,12 @@ static void cpm2_unmask_irq(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(cpm2_immr->im_intctl.ic_simrh);
+	simr = &(immr->im_intctl.ic_simrh);
 	ppc_cached_irq_mask[word] |= (1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 }
 
-static void cpm2_mask_and_ack(unsigned int irq_nr)
+static void m8260_mask_and_ack(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr, *sipnr;
@@ -74,14 +74,14 @@ static void cpm2_mask_and_ack(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(cpm2_immr->im_intctl.ic_simrh);
-	sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
+	simr = &(immr->im_intctl.ic_simrh);
+	sipnr = &(immr->im_intctl.ic_sipnrh);
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 	sipnr[word] = 1 << (31 - bit);
 }
 
-static void cpm2_end_irq(unsigned int irq_nr)
+static void m8260_end_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -92,33 +92,33 @@ static void cpm2_end_irq(unsigned int irq_nr)
 		bit = irq_to_siubit[irq_nr];
 		word = irq_to_siureg[irq_nr];
 
-		simr = &(cpm2_immr->im_intctl.ic_simrh);
+		simr = &(immr->im_intctl.ic_simrh);
 		ppc_cached_irq_mask[word] |= (1 << (31 - bit));
 		simr[word] = ppc_cached_irq_mask[word];
 	}
 }
 
-struct hw_interrupt_type cpm2_pic = {
-	" CPM2 SIU  ",
+struct hw_interrupt_type ppc8260_pic = {
+	" 8260 SIU  ",
 	NULL,
 	NULL,
-	cpm2_unmask_irq,
-	cpm2_mask_irq,
-	cpm2_mask_and_ack,
-	cpm2_end_irq,
+	m8260_unmask_irq,
+	m8260_mask_irq,
+	m8260_mask_and_ack,
+	m8260_end_irq,
 	0
 };
 
 
 int
-cpm2_get_irq(struct pt_regs *regs)
+m8260_get_irq(struct pt_regs *regs)
 {
 	int irq;
         unsigned long bits;
 
-        /* For CPM2, read the SIVEC register and shift the bits down
+        /* For MPC8260, read the SIVEC register and shift the bits down
          * to get the irq number.         */
-        bits = cpm2_immr->im_intctl.ic_sivec;
+        bits = immr->im_intctl.ic_sivec;
         irq = bits >> 26;
 
 	if (irq == 0)