X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fppc%2Fsyslib%2Fqspan_pci.c;h=85053b2816a9dd9a40a394ca5cc7299118f13953;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=57edf3a272d5c1f0c4ca394e66b9282a8059b05d;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git

diff --git a/arch/ppc/syslib/qspan_pci.c b/arch/ppc/syslib/qspan_pci.c
index 57edf3a27..85053b281 100644
--- a/arch/ppc/syslib/qspan_pci.c
+++ b/arch/ppc/syslib/qspan_pci.c
@@ -15,7 +15,6 @@
  * we have switched the chip select.
  */
 
-#include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/delay.h>
@@ -94,6 +93,8 @@
 #define mk_config_type1(bus, dev, offset) \
 	mk_config_addr(bus, dev, offset) | 1;
 
+static DEFINE_SPINLOCK(pcibios_lock);
+
 int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
 				  unsigned char offset, unsigned char *val)
 {
@@ -109,8 +110,8 @@ int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
 	}
 
 #ifdef CONFIG_RPXCLASSIC
-	save_flags(flags);
-	cli();
+	/* disable interrupts */
+	spin_lock_irqsave(&pcibios_lock, flags);
 	*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
 	eieio();
 #endif
@@ -124,7 +125,7 @@ int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
 #ifdef CONFIG_RPXCLASSIC
 	*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
 	eieio();
-	restore_flags(flags);
+	spin_unlock_irqrestore(&pcibios_lock, flags);
 #endif
 
 	offset ^= 0x03;
@@ -148,8 +149,8 @@ int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
 	}
 
 #ifdef CONFIG_RPXCLASSIC
-	save_flags(flags);
-	cli();
+	/* disable interrupts */
+	spin_lock_irqsave(&pcibios_lock, flags);
 	*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
 	eieio();
 #endif
@@ -164,7 +165,7 @@ int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
 #ifdef CONFIG_RPXCLASSIC
 	*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
 	eieio();
-	restore_flags(flags);
+	spin_unlock_irqrestore(&pcibios_lock, flags);
 #endif
 
 	sp = ((ushort *)&temp) + ((offset >> 1) & 1);
@@ -185,8 +186,8 @@ int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
 	}
 
 #ifdef CONFIG_RPXCLASSIC
-	save_flags(flags);
-	cli();
+	/* disable interrupts */
+	spin_lock_irqsave(&pcibios_lock, flags);
 	*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
 	eieio();
 #endif
@@ -200,7 +201,7 @@ int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
 #ifdef CONFIG_RPXCLASSIC
 	*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
 	eieio();
-	restore_flags(flags);
+	spin_unlock_irqrestore(&pcibios_lock, flags);
 #endif
 
 	return PCIBIOS_SUCCESSFUL;
@@ -225,8 +226,8 @@ int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
 	*cp = val;
 
 #ifdef CONFIG_RPXCLASSIC
-	save_flags(flags);
-	cli();
+	/* disable interrupts */
+	spin_lock_irqsave(&pcibios_lock, flags);
 	*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
 	eieio();
 #endif
@@ -240,7 +241,7 @@ int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
 #ifdef CONFIG_RPXCLASSIC
 	*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
 	eieio();
-	restore_flags(flags);
+	spin_unlock_irqrestore(&pcibios_lock, flags);
 #endif
 
 	return PCIBIOS_SUCCESSFUL;
@@ -265,8 +266,8 @@ int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
 	*sp = val;
 
 #ifdef CONFIG_RPXCLASSIC
-	save_flags(flags);
-	cli();
+	/* disable interrupts */
+	spin_lock_irqsave(&pcibios_lock, flags);
 	*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
 	eieio();
 #endif
@@ -280,7 +281,7 @@ int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
 #ifdef CONFIG_RPXCLASSIC
 	*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
 	eieio();
-	restore_flags(flags);
+	spin_unlock_irqrestore(&pcibios_lock, flags);
 #endif
 
 	return PCIBIOS_SUCCESSFUL;
@@ -297,8 +298,8 @@ int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 #ifdef CONFIG_RPXCLASSIC
-	save_flags(flags);
-	cli();
+	/* disable interrupts */
+	spin_lock_irqsave(&pcibios_lock, flags);
 	*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
 	eieio();
 #endif
@@ -312,7 +313,7 @@ int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
 #ifdef CONFIG_RPXCLASSIC
 	*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
 	eieio();
-	restore_flags(flags);
+	spin_unlock_irqrestore(&pcibios_lock, flags);
 #endif
 
 	return PCIBIOS_SUCCESSFUL;