X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fsparc64%2Fkernel%2Fpci.c;h=bba140d98b1b8c1802664f625b102fb532339f9d;hb=f7f1b0f1e2fbadeab12d24236000e778aa9b1ead;hp=2ffd1efefcc09bec7b1d8fd406bbac6b9dcd258b;hpb=e3f6fb6212a7102bdb56ba38fa1e98fe72950475;p=linux-2.6.git diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c index 2ffd1efef..bba140d98 100644 --- a/arch/sparc64/kernel/pci.c +++ b/arch/sparc64/kernel/pci.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -734,12 +735,10 @@ static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state) { - /* Our io_remap_page_range takes care of this, do nothing. */ + /* Our io_remap_page_range/io_remap_pfn_range takes care of this, + do nothing. */ } -extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, unsigned long offset, - unsigned long size, pgprot_t prot, int space); - /* Perform the actual remap of the pages for a PCI device mapping, as appropriate * for this architecture. The region in the process to map is described by vm_start * and vm_end members of VMA, the base physical address is found in vm_pgoff. @@ -761,10 +760,10 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, __pci_mmap_set_flags(dev, vma, mmap_state); __pci_mmap_set_pgprot(dev, vma, mmap_state); - ret = io_remap_page_range(vma, vma->vm_start, - (vma->vm_pgoff << PAGE_SHIFT | - (write_combine ? 0x1UL : 0x0UL)), - vma->vm_end - vma->vm_start, vma->vm_page_prot, 0); + ret = io_remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot); if (ret) return ret; @@ -794,12 +793,6 @@ int pci_domain_nr(struct pci_bus *pbus) } EXPORT_SYMBOL(pci_domain_nr); -int pci_name_bus(char *name, struct pci_bus *bus) -{ - sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number); - return 0; -} - int pcibios_prep_mwi(struct pci_dev *dev) { /* We set correct PCI_CACHE_LINE_SIZE register values for every