X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=arch%2Fx86_64%2Fkernel%2Fsuspend.c;h=ecbd34c1093d0a03109a9c99fe7c9c1c61cf646a;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=d8cdbe131c73b7963548404eed9c1e684f31c6d9;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/arch/x86_64/kernel/suspend.c b/arch/x86_64/kernel/suspend.c index d8cdbe131..ecbd34c10 100644 --- a/arch/x86_64/kernel/suspend.c +++ b/arch/x86_64/kernel/suspend.c @@ -8,24 +8,11 @@ */ #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include -#include -#include -#include -#include #include +#include +#include struct saved_context saved_context; @@ -35,95 +22,105 @@ unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_con unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15; unsigned long saved_context_eflags; -void save_processor_state (void) +void __save_processor_state(struct saved_context *ctxt) { kernel_fpu_begin(); /* * descriptor tables */ - asm volatile ("sgdt %0" : "=m" (saved_context.gdt_limit)); - asm volatile ("sidt %0" : "=m" (saved_context.idt_limit)); - asm volatile ("sldt %0" : "=m" (saved_context.ldt)); - asm volatile ("str %0" : "=m" (saved_context.tr)); + asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit)); + asm volatile ("sidt %0" : "=m" (ctxt->idt_limit)); + asm volatile ("str %0" : "=m" (ctxt->tr)); /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ /* EFER should be constant for kernel version, no need to handle it. */ /* * segment registers */ - asm volatile ("movw %%ds, %0" : "=m" (saved_context.ds)); - asm volatile ("movw %%es, %0" : "=m" (saved_context.es)); - asm volatile ("movw %%fs, %0" : "=m" (saved_context.fs)); - asm volatile ("movw %%gs, %0" : "=m" (saved_context.gs)); - asm volatile ("movw %%ss, %0" : "=m" (saved_context.ss)); + asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds)); + asm volatile ("movw %%es, %0" : "=m" (ctxt->es)); + asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs)); + asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs)); + asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss)); - rdmsrl(MSR_FS_BASE, saved_context.fs_base); - rdmsrl(MSR_GS_BASE, saved_context.gs_base); - rdmsrl(MSR_KERNEL_GS_BASE, saved_context.gs_kernel_base); + rdmsrl(MSR_FS_BASE, ctxt->fs_base); + rdmsrl(MSR_GS_BASE, ctxt->gs_base); + rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); /* * control registers */ - asm volatile ("movq %%cr0, %0" : "=r" (saved_context.cr0)); - asm volatile ("movq %%cr2, %0" : "=r" (saved_context.cr2)); - asm volatile ("movq %%cr3, %0" : "=r" (saved_context.cr3)); - asm volatile ("movq %%cr4, %0" : "=r" (saved_context.cr4)); + asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0)); + asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2)); + asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3)); + asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4)); + asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8)); } -static void -do_fpu_end(void) +void save_processor_state(void) { - /* restore FPU regs if necessary */ - /* Do it out of line so that gcc does not move cr0 load to some stupid place */ - kernel_fpu_end(); - mxcsr_feature_mask_init(); + __save_processor_state(&saved_context); } -void restore_processor_state(void) +static void do_fpu_end(void) { /* - * control registers + * Restore FPU regs if necessary */ - asm volatile ("movq %0, %%cr4" :: "r" (saved_context.cr4)); - asm volatile ("movq %0, %%cr3" :: "r" (saved_context.cr3)); - asm volatile ("movq %0, %%cr2" :: "r" (saved_context.cr2)); - asm volatile ("movq %0, %%cr0" :: "r" (saved_context.cr0)); + kernel_fpu_end(); +} +void __restore_processor_state(struct saved_context *ctxt) +{ /* - * segment registers + * control registers */ - asm volatile ("movw %0, %%ds" :: "r" (saved_context.ds)); - asm volatile ("movw %0, %%es" :: "r" (saved_context.es)); - asm volatile ("movw %0, %%fs" :: "r" (saved_context.fs)); - load_gs_index(saved_context.gs); - asm volatile ("movw %0, %%ss" :: "r" (saved_context.ss)); - - wrmsrl(MSR_FS_BASE, saved_context.fs_base); - wrmsrl(MSR_GS_BASE, saved_context.gs_base); - wrmsrl(MSR_KERNEL_GS_BASE, saved_context.gs_kernel_base); + asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8)); + asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4)); + asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3)); + asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2)); + asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0)); /* * now restore the descriptor tables to their proper values * ltr is done i fix_processor_context(). */ - asm volatile ("lgdt %0" :: "m" (saved_context.gdt_limit)); - asm volatile ("lidt %0" :: "m" (saved_context.idt_limit)); - asm volatile ("lldt %0" :: "m" (saved_context.ldt)); + asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit)); + asm volatile ("lidt %0" :: "m" (ctxt->idt_limit)); + + /* + * segment registers + */ + asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); + asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); + asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); + load_gs_index(ctxt->gs); + asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); + + wrmsrl(MSR_FS_BASE, ctxt->fs_base); + wrmsrl(MSR_GS_BASE, ctxt->gs_base); + wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); fix_processor_context(); do_fpu_end(); + mtrr_ap_init(); +} + +void restore_processor_state(void) +{ + __restore_processor_state(&saved_context); } void fix_processor_context(void) { int cpu = smp_processor_id(); - struct tss_struct * t = init_tss + cpu; + struct tss_struct *t = &per_cpu(init_tss, cpu); set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */ - cpu_gdt_table[cpu][GDT_ENTRY_TSS].type = 9; + cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9; syscall_init(); /* This sets MSR_*STAR and related */ load_TR_desc(); /* This does ltr */ @@ -144,4 +141,83 @@ void fix_processor_context(void) } +#ifdef CONFIG_SOFTWARE_SUSPEND +/* Defined in arch/x86_64/kernel/suspend_asm.S */ +extern int restore_image(void); + +pgd_t *temp_level4_pgt; + +static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end) +{ + long i, j; + + i = pud_index(address); + pud = pud + i; + for (; i < PTRS_PER_PUD; pud++, i++) { + unsigned long paddr; + pmd_t *pmd; + + paddr = address + i*PUD_SIZE; + if (paddr >= end) + break; + + pmd = (pmd_t *)get_safe_page(GFP_ATOMIC); + if (!pmd) + return -ENOMEM; + set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); + for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) { + unsigned long pe; + + if (paddr >= end) + break; + pe = _PAGE_NX | _PAGE_PSE | _KERNPG_TABLE | paddr; + pe &= __supported_pte_mask; + set_pmd(pmd, __pmd(pe)); + } + } + return 0; +} + +static int set_up_temporary_mappings(void) +{ + unsigned long start, end, next; + int error; + + temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC); + if (!temp_level4_pgt) + return -ENOMEM; + + /* It is safe to reuse the original kernel mapping */ + set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map), + init_level4_pgt[pgd_index(__START_KERNEL_map)]); + + /* Set up the direct mapping from scratch */ + start = (unsigned long)pfn_to_kaddr(0); + end = (unsigned long)pfn_to_kaddr(end_pfn); + + for (; start < end; start = next) { + pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC); + if (!pud) + return -ENOMEM; + next = start + PGDIR_SIZE; + if (next > end) + next = end; + if ((error = res_phys_pud_init(pud, __pa(start), __pa(next)))) + return error; + set_pgd(temp_level4_pgt + pgd_index(start), + mk_kernel_pgd(__pa(pud))); + } + return 0; +} + +int swsusp_arch_resume(void) +{ + int error; + /* We have got enough memory and from now on we cannot recover */ + if ((error = set_up_temporary_mappings())) + return error; + restore_image(); + return 0; +} +#endif /* CONFIG_SOFTWARE_SUSPEND */