X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fatm%2Fiphase.h;h=133eefcc047507376977417dd056ae6bf4de8ea9;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=9da028683bb8a6c28557d4a623d73bf86fff14eb;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git

diff --git a/drivers/atm/iphase.h b/drivers/atm/iphase.h
index 9da028683..133eefcc0 100644
--- a/drivers/atm/iphase.h
+++ b/drivers/atm/iphase.h
@@ -43,7 +43,6 @@
 #ifndef IPHASE_H  
 #define IPHASE_H  
 
-#include <linux/config.h>
 
 /************************ IADBG DEFINE *********************************/
 /* IADebugFlag Bit Map */ 
@@ -996,18 +995,18 @@ typedef struct _SUNI_STATS_
 
 typedef struct iadev_t {  
 	/*-----base pointers into (i)chipSAR+ address space */   
-	u32 *phy;			/* base pointer into phy(SUNI) */  
-	u32 *dma;			/* base pointer into DMA control   
+	u32 __iomem *phy;		/* base pointer into phy(SUNI) */  
+	u32 __iomem *dma;		/* base pointer into DMA control   
 						registers */  
-	u32 *reg;			/* base pointer to SAR registers  
+	u32 __iomem *reg;		/* base pointer to SAR registers  
 					   - Bus Interface Control Regs */  
-	u32 *seg_reg;			/* base pointer to segmentation engine  
+	u32 __iomem *seg_reg;		/* base pointer to segmentation engine  
 						internal registers */  
-	u32 *reass_reg;			/* base pointer to reassemble engine  
+	u32 __iomem *reass_reg;		/* base pointer to reassemble engine  
 						internal registers */  
-	u32 *ram;			/* base pointer to SAR RAM */  
-	unsigned int seg_ram;  
-	unsigned int reass_ram;  
+	u32 __iomem *ram;		/* base pointer to SAR RAM */  
+	void __iomem *seg_ram;  
+	void __iomem *reass_ram;  
 	struct dle_q tx_dle_q;  
 	struct free_desc_q *tx_free_desc_qhead;  
 	struct sk_buff_head tx_dma_q, tx_backlog;  
@@ -1019,7 +1018,7 @@ typedef struct iadev_t {
 	struct cpcs_trailer_desc *tx_buf;
         u16 num_tx_desc, tx_buf_sz, rate_limit;
         u32 tx_cell_cnt, tx_pkt_cnt;
-        u32 MAIN_VC_TABLE_ADDR, EXT_VC_TABLE_ADDR, ABR_SCHED_TABLE_ADDR;
+        void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
 	struct dle_q rx_dle_q;  
 	struct free_desc_q *rx_free_desc_qhead;  
 	struct sk_buff_head rx_dma_q;  
@@ -1027,13 +1026,13 @@ typedef struct iadev_t {
 	struct atm_vcc **rx_open;	/* list of all open VCs */  
         u16 num_rx_desc, rx_buf_sz, rxing;
         u32 rx_pkt_ram, rx_tmp_cnt, rx_tmp_jif;
-        u32 RX_DESC_BASE_ADDR;
+        void __iomem *RX_DESC_BASE_ADDR;
         u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
 	struct atm_dev *next_board;	/* other iphase devices */  
 	struct pci_dev *pci;  
 	int mem;  
-	unsigned long base_diff;	/* virtual - real base address */  
-	unsigned int real_base, base;	/* real and virtual base address */  
+	unsigned int real_base;	/* real and virtual base address */  
+	void __iomem *base;
 	unsigned int pci_map_size;	/*pci map size of board */  
 	unsigned char irq;  
 	unsigned char bus;  
@@ -1126,8 +1125,6 @@ typedef struct {
 #define FE_DS3_PHY      0x0080          /* DS3 */
 #define FE_E3_PHY       0x0090          /* E3 */
 		     
-extern void ia_mb25_init (IADEV *);
-
 /*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
 typedef struct _suni_pm7345_t
 {
@@ -1326,8 +1323,6 @@ typedef struct _suni_pm7345_t
 #define SUNI_DS3_FOVRI  0x02            /* FIFO overrun                 */
 #define SUNI_DS3_FUDRI  0x01            /* FIFO underrun                */
 
-extern void ia_suni_pm7345_init (IADEV *iadev);
-
 ///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////
 
 /* ia_eeprom define*/