X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fchar%2Fagp%2Fhp-agp.c;h=3f8c2d41b0ee28dc7f2725b482c479c03f39f214;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=323a6b68d79e55a6c2b077c1ab9013213ddccf3a;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git

diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c
index 323a6b68d..3f8c2d41b 100644
--- a/drivers/char/agp/hp-agp.c
+++ b/drivers/char/agp/hp-agp.c
@@ -88,7 +88,7 @@ static int __init hp_zx1_ioc_shared(void)
 	 * 	- IOVA space is 1Gb in size
 	 * 	- first 512Mb is IOMMU, second 512Mb is GART
 	 */
-	hp->io_tlb_ps = INREG64(hp->ioc_regs, HP_ZX1_TCNFG);
+	hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
 	switch (hp->io_tlb_ps) {
 		case 0: hp->io_tlb_shift = 12; break;
 		case 1: hp->io_tlb_shift = 13; break;
@@ -104,13 +104,13 @@ static int __init hp_zx1_ioc_shared(void)
 	hp->io_page_size = 1 << hp->io_tlb_shift;
 	hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
 
-	hp->iova_base = INREG64(hp->ioc_regs, HP_ZX1_IBASE) & ~0x1;
+	hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
 	hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;
 
 	hp->gart_size = HP_ZX1_GART_SIZE;
 	hp->gatt_entries = hp->gart_size / hp->io_page_size;
 
-	hp->io_pdir = phys_to_virt(INREG64(hp->ioc_regs, HP_ZX1_PDIR_BASE));
+	hp->io_pdir = phys_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
 	hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
 
 	if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
@@ -174,7 +174,7 @@ hp_zx1_ioc_init (u64 hpa)
 	 * If the IOTLB is currently disabled, we can take it over.
 	 * Otherwise, we have to share with sba_iommu.
 	 */
-	hp->io_pdir_owner = (INREG64(hp->ioc_regs, HP_ZX1_IBASE) & 0x1) == 0;
+	hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;
 
 	if (hp->io_pdir_owner)
 		return hp_zx1_ioc_owner();
@@ -189,18 +189,18 @@ hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap)
 	u8 pos, id;
 	int ttl = 48;
 
-	status = INREG16(hpa, PCI_STATUS);
+	status = readw(hpa+PCI_STATUS);
 	if (!(status & PCI_STATUS_CAP_LIST))
 		return 0;
-	pos = INREG8(hpa, PCI_CAPABILITY_LIST);
+	pos = readb(hpa+PCI_CAPABILITY_LIST);
 	while (ttl-- && pos >= 0x40) {
 		pos &= ~3;
-		id = INREG8(hpa, pos + PCI_CAP_LIST_ID);
+		id = readb(hpa+pos+PCI_CAP_LIST_ID);
 		if (id == 0xff)
 			break;
 		if (id == cap)
 			return pos;
-		pos = INREG8(hpa, pos + PCI_CAP_LIST_NEXT);
+		pos = readb(hpa+pos+PCI_CAP_LIST_NEXT);
 	}
 	return 0;
 }
@@ -217,7 +217,7 @@ hp_zx1_lba_init (u64 hpa)
 
 	hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);
 
-	cap = INREG32(hp->lba_regs, hp->lba_cap_offset) & 0xff;
+	cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff;
 	if (cap != PCI_CAP_ID_AGP) {
 		printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
 		       cap, hp->lba_cap_offset);
@@ -245,15 +245,19 @@ hp_zx1_configure (void)
 
 	agp_bridge->gart_bus_addr = hp->gart_base;
 	agp_bridge->capndx = hp->lba_cap_offset;
-	agp_bridge->mode = INREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_STATUS);
+	agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
 
 	if (hp->io_pdir_owner) {
-		OUTREG64(hp->ioc_regs, HP_ZX1_PDIR_BASE, virt_to_phys(hp->io_pdir));
-		OUTREG64(hp->ioc_regs, HP_ZX1_TCNFG, hp->io_tlb_ps);
-		OUTREG64(hp->ioc_regs, HP_ZX1_IMASK, ~(HP_ZX1_IOVA_SIZE - 1));
-		OUTREG64(hp->ioc_regs, HP_ZX1_IBASE, hp->iova_base | 0x1);
-		OUTREG64(hp->ioc_regs, HP_ZX1_PCOM, hp->iova_base | log2(HP_ZX1_IOVA_SIZE));
-		INREG64(hp->ioc_regs, HP_ZX1_PCOM);
+		writel(virt_to_phys(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE);
+		readl(hp->ioc_regs+HP_ZX1_PDIR_BASE);
+		writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG);
+		readl(hp->ioc_regs+HP_ZX1_TCNFG);
+		writel(~(HP_ZX1_IOVA_SIZE-1), hp->ioc_regs+HP_ZX1_IMASK);
+		readl(hp->ioc_regs+HP_ZX1_IMASK);
+		writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE);
+		readl(hp->ioc_regs+HP_ZX1_IBASE);
+		writel(hp->iova_base|log2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM);
+		readl(hp->ioc_regs+HP_ZX1_PCOM);
 	}
 
 	return 0;
@@ -265,8 +269,10 @@ hp_zx1_cleanup (void)
 	struct _hp_private *hp = &hp_private;
 
 	if (hp->ioc_regs) {
-		if (hp->io_pdir_owner)
-			OUTREG64(hp->ioc_regs, HP_ZX1_IBASE, 0);
+		if (hp->io_pdir_owner) {
+			writeq(0, hp->ioc_regs+HP_ZX1_IBASE);
+			readq(hp->ioc_regs+HP_ZX1_IBASE);
+		}
 		iounmap(hp->ioc_regs);
 	}
 	if (hp->lba_regs)
@@ -278,8 +284,8 @@ hp_zx1_tlbflush (struct agp_memory *mem)
 {
 	struct _hp_private *hp = &hp_private;
 
-	OUTREG64(hp->ioc_regs, HP_ZX1_PCOM, hp->gart_base | log2(hp->gart_size));
-	INREG64(hp->ioc_regs, HP_ZX1_PCOM);
+	writeq(hp->gart_base | log2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM);
+	readq(hp->ioc_regs+HP_ZX1_PCOM);
 }
 
 static int
@@ -401,12 +407,11 @@ hp_zx1_enable (u32 mode)
 	struct _hp_private *hp = &hp_private;
 	u32 command;
 
-	command = INREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_STATUS);
-
+	command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
 	command = agp_collect_device_status(mode, command);
 	command |= 0x00000100;
 
-	OUTREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_COMMAND, command);
+	writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
 
 	agp_device_command(command, (mode & AGP8X_MODE) != 0);
 }
@@ -519,6 +524,8 @@ zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret)
 static int __init
 agp_hp_init (void)
 {
+	if (agp_off)
+		return -EINVAL;
 
 	acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
 	if (hp_zx1_gart_found)