X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fedac%2Fr82600_edac.c;h=a49cf0a39398a4476e37c7105c02b6a3123daee4;hb=refs%2Fheads%2Fvserver;hp=e90892831b90e9e857b6f517cd98a9cb77362bbe;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c index e90892831..a49cf0a39 100644 --- a/drivers/edac/r82600_edac.c +++ b/drivers/edac/r82600_edac.c @@ -15,17 +15,22 @@ * references to this document given in [] */ -#include #include #include - #include #include - #include - #include "edac_mc.h" +#define R82600_REVISION " Ver: 2.0.1 " __DATE__ +#define EDAC_MOD_STR "r82600_edac" + +#define r82600_printk(level, fmt, arg...) \ + edac_printk(level, "r82600", fmt, ##arg) + +#define r82600_mc_printk(mci, level, fmt, arg...) \ + edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) + /* Radisys say "The 82600 integrates a main memory SDRAM controller that * supports up to four banks of memory. The four banks can support a mix of * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, @@ -126,29 +131,29 @@ struct r82600_error_info { u32 eapr; }; - static unsigned int disable_hardware_scrub = 0; - static void r82600_get_error_info (struct mem_ctl_info *mci, struct r82600_error_info *info) { - pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr); + struct pci_dev *pdev; + + pdev = to_pci_dev(mci->dev); + pci_read_config_dword(pdev, R82600_EAP, &info->eapr); if (info->eapr & BIT(0)) /* Clear error to allow next error to be reported [p.62] */ - pci_write_bits32(mci->pdev, R82600_EAP, - ((u32) BIT(0) & (u32) BIT(1)), - ((u32) BIT(0) & (u32) BIT(1))); + pci_write_bits32(pdev, R82600_EAP, + ((u32) BIT(0) & (u32) BIT(1)), + ((u32) BIT(0) & (u32) BIT(1))); if (info->eapr & BIT(1)) /* Clear error to allow next error to be reported [p.62] */ - pci_write_bits32(mci->pdev, R82600_EAP, - ((u32) BIT(0) & (u32) BIT(1)), - ((u32) BIT(0) & (u32) BIT(1))); + pci_write_bits32(pdev, R82600_EAP, + ((u32) BIT(0) & (u32) BIT(1)), + ((u32) BIT(0) & (u32) BIT(1))); } - static int r82600_process_error_info (struct mem_ctl_info *mci, struct r82600_error_info *info, int handle_errors) { @@ -167,26 +172,25 @@ static int r82600_process_error_info (struct mem_ctl_info *mci, * granularity (upper 19 bits only) */ page = eapaddr >> PAGE_SHIFT; - if (info->eapr & BIT(0)) { /* CE? */ + if (info->eapr & BIT(0)) { /* CE? */ error_found = 1; if (handle_errors) - edac_mc_handle_ce( - mci, page, 0, /* not avail */ - syndrome, - edac_mc_find_csrow_by_page(mci, page), - 0, /* channel */ - mci->ctl_name); + edac_mc_handle_ce(mci, page, 0, /* not avail */ + syndrome, + edac_mc_find_csrow_by_page(mci, page), + 0, /* channel */ + mci->ctl_name); } - if (info->eapr & BIT(1)) { /* UE? */ + if (info->eapr & BIT(1)) { /* UE? */ error_found = 1; if (handle_errors) /* 82600 doesn't give enough info */ edac_mc_handle_ue(mci, page, 0, - edac_mc_find_csrow_by_page(mci, page), - mci->ctl_name); + edac_mc_find_csrow_by_page(mci, page), + mci->ctl_name); } return error_found; @@ -196,96 +200,42 @@ static void r82600_check(struct mem_ctl_info *mci) { struct r82600_error_info info; - debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__); + debugf1("MC%d: %s()\n", mci->mc_idx, __func__); r82600_get_error_info(mci, &info); r82600_process_error_info(mci, &info, 1); } -static int r82600_probe1(struct pci_dev *pdev, int dev_idx) +static inline int ecc_enabled(u8 dramcr) { - int rc = -ENODEV; - int index; - struct mem_ctl_info *mci = NULL; - u8 dramcr; - u32 ecc_on; - u32 reg_sdram; - u32 eapr; - u32 scrub_disabled; - u32 sdram_refresh_rate; - u32 row_high_limit_last = 0; - u32 eap_init_bits; - - debugf0("MC: " __FILE__ ": %s()\n", __func__); - + return dramcr & BIT(5); +} - pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); - pci_read_config_dword(pdev, R82600_EAP, &eapr); +static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, + u8 dramcr) +{ + struct csrow_info *csrow; + int index; + u8 drbar; /* SDRAM Row Boundry Address Register */ + u32 row_high_limit, row_high_limit_last; + u32 reg_sdram, ecc_on, row_base; - ecc_on = dramcr & BIT(5); + ecc_on = ecc_enabled(dramcr); reg_sdram = dramcr & BIT(4); - scrub_disabled = eapr & BIT(31); - sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); - - debugf2("MC: " __FILE__ ": %s(): sdram refresh rate = %#0x\n", - __func__, sdram_refresh_rate); - - debugf2("MC: " __FILE__ ": %s(): DRAMC register = %#0x\n", __func__, - dramcr); - - mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS); - - if (mci == NULL) { - rc = -ENOMEM; - goto fail; - } - - debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); - - mci->pdev = pdev; - mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; - - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; - /* FIXME try to work out if the chip leads have been * - * used for COM2 instead on this board? [MA6?] MAYBE: */ - - /* On the R82600, the pins for memory bits 72:65 - i.e. the * - * EC bits are shared with the pins for COM2 (!), so if COM2 * - * is enabled, we assume COM2 is wired up, and thus no EDAC * - * is possible. */ - mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; - if (ecc_on) { - if (scrub_disabled) - debugf3("MC: " __FILE__ ": %s(): mci = %p - " - "Scrubbing disabled! EAP: %#0x\n", __func__, - mci, eapr); - } else - mci->edac_cap = EDAC_FLAG_NONE; - - mci->mod_name = BS_MOD_STR; - mci->mod_ver = "$Revision: 1.1.2.6 $"; - mci->ctl_name = "R82600"; - mci->edac_check = r82600_check; - mci->ctl_page_to_phys = NULL; + row_high_limit_last = 0; for (index = 0; index < mci->nr_csrows; index++) { - struct csrow_info *csrow = &mci->csrows[index]; - u8 drbar; /* sDram Row Boundry Address Register */ - u32 row_high_limit; - u32 row_base; + csrow = &mci->csrows[index]; /* find the DRAM Chip Select Base address and mask */ - pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar); + pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); - debugf1("MC%d: " __FILE__ ": %s() Row=%d DRBA = %#0x\n", - mci->mc_idx, __func__, index, drbar); + debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar); row_high_limit = ((u32) drbar << 24); /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ - debugf1("MC%d: " __FILE__ ": %s() Row=%d, " - "Boundry Address=%#0x, Last = %#0x \n", - mci->mc_idx, __func__, index, row_high_limit, - row_high_limit_last); + debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n", + __func__, index, row_high_limit, row_high_limit_last); /* Empty row [p.57] */ if (row_high_limit == row_high_limit_last) @@ -307,99 +257,139 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx) csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; row_high_limit_last = row_high_limit; } +} + +static int r82600_probe1(struct pci_dev *pdev, int dev_idx) +{ + struct mem_ctl_info *mci; + u8 dramcr; + u32 eapr; + u32 scrub_disabled; + u32 sdram_refresh_rate; + struct r82600_error_info discard; + + debugf0("%s()\n", __func__); + pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); + pci_read_config_dword(pdev, R82600_EAP, &eapr); + scrub_disabled = eapr & BIT(31); + sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); + debugf2("%s(): sdram refresh rate = %#0x\n", __func__, + sdram_refresh_rate); + debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr); + mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS); + + if (mci == NULL) + return -ENOMEM; + + debugf0("%s(): mci = %p\n", __func__, mci); + mci->dev = &pdev->dev; + mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; + /* FIXME try to work out if the chip leads have been used for COM2 + * instead on this board? [MA6?] MAYBE: + */ - /* clear counters */ - /* FIXME should we? */ + /* On the R82600, the pins for memory bits 72:65 - i.e. the * + * EC bits are shared with the pins for COM2 (!), so if COM2 * + * is enabled, we assume COM2 is wired up, and thus no EDAC * + * is possible. */ + mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; + + if (ecc_enabled(dramcr)) { + if (scrub_disabled) + debugf3("%s(): mci = %p - Scrubbing disabled! EAP: " + "%#0x\n", __func__, mci, eapr); + } else + mci->edac_cap = EDAC_FLAG_NONE; - if (edac_mc_add_mc(mci)) { - debugf3("MC: " __FILE__ - ": %s(): failed edac_mc_add_mc()\n", __func__); + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = R82600_REVISION; + mci->ctl_name = "R82600"; + mci->edac_check = r82600_check; + mci->ctl_page_to_phys = NULL; + r82600_init_csrows(mci, pdev, dramcr); + r82600_get_error_info(mci, &discard); /* clear counters */ + + /* Here we assume that we will never see multiple instances of this + * type of memory controller. The ID is therefore hardcoded to 0. + */ + if (edac_mc_add_mc(mci,0)) { + debugf3("%s(): failed edac_mc_add_mc()\n", __func__); goto fail; } /* get this far and it's successful */ - /* Clear error flags to allow next error to be reported [p.62] */ - /* Test systems seem to always have the UE flag raised on boot */ - - eap_init_bits = BIT(0) & BIT(1); if (disable_hardware_scrub) { - eap_init_bits |= BIT(31); - debugf3("MC: " __FILE__ ": %s(): Disabling Hardware Scrub " - "(scrub on error)\n", __func__); + debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n", + __func__); + pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); } - pci_write_bits32(mci->pdev, R82600_EAP, eap_init_bits, - eap_init_bits); - - debugf3("MC: " __FILE__ ": %s(): success\n", __func__); + debugf3("%s(): success\n", __func__); return 0; fail: - if (mci) - edac_mc_free(mci); - - return rc; + edac_mc_free(mci); + return -ENODEV; } /* returns count (>= 0), or negative on error */ static int __devinit r82600_init_one(struct pci_dev *pdev, - const struct pci_device_id *ent) + const struct pci_device_id *ent) { - debugf0("MC: " __FILE__ ": %s()\n", __func__); + debugf0("%s()\n", __func__); /* don't need to call pci_device_enable() */ return r82600_probe1(pdev, ent->driver_data); } - static void __devexit r82600_remove_one(struct pci_dev *pdev) { struct mem_ctl_info *mci; - debugf0(__FILE__ ": %s()\n", __func__); + debugf0("%s()\n", __func__); - if (((mci = edac_mc_find_mci_by_pdev(pdev)) != NULL) && - !edac_mc_del_mc(mci)) - edac_mc_free(mci); -} + if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) + return; + edac_mc_free(mci); +} static const struct pci_device_id r82600_pci_tbl[] __devinitdata = { - {PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)}, - {0,} /* 0 terminated list. */ + { + PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) + }, + { + 0, + } /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); - static struct pci_driver r82600_driver = { - .name = BS_MOD_STR, + .name = EDAC_MOD_STR, .probe = r82600_init_one, .remove = __devexit_p(r82600_remove_one), .id_table = r82600_pci_tbl, }; - static int __init r82600_init(void) { return pci_register_driver(&r82600_driver); } - static void __exit r82600_exit(void) { pci_unregister_driver(&r82600_driver); } - module_init(r82600_init); module_exit(r82600_exit); - MODULE_LICENSE("GPL"); MODULE_AUTHOR("Tim Small - WPAD Ltd. " - "on behalf of EADS Astrium"); + "on behalf of EADS Astrium"); MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); module_param(disable_hardware_scrub, bool, 0644);