X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fmedia%2Fvideo%2Fcx88%2Fcx88-reg.h;h=d3bf5b17b1d40dde2a2b1f2d28b4c80bfbfd7966;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=4ecce88a85d41452f7bc09ec3a7766f010e1763e;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/drivers/media/video/cx88/cx88-reg.h b/drivers/media/video/cx88/cx88-reg.h index 4ecce88a8..d3bf5b17b 100644 --- a/drivers/media/video/cx88/cx88-reg.h +++ b/drivers/media/video/cx88/cx88-reg.h @@ -1,10 +1,11 @@ -/* +/* + cx88x-hw.h - CX2388x register offsets Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de) - 2001 Michael Eskin - 2002 Yurij Sysoev - 2003 Gerd Knorr + 2001 Michael Eskin + 2002 Yurij Sysoev + 2003 Gerd Knorr This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -38,6 +39,29 @@ #define CX88X_EN_TBFX 0x02 #define CX88X_EN_VSFX 0x04 +/* ---------------------------------------------------------------------- */ +/* PCI controller registers */ + +/* Command and Status Register */ +#define F0_CMD_STAT_MM 0x2f0004 +#define F1_CMD_STAT_MM 0x2f0104 +#define F2_CMD_STAT_MM 0x2f0204 +#define F3_CMD_STAT_MM 0x2f0304 +#define F4_CMD_STAT_MM 0x2f0404 + +/* Device Control #1 */ +#define F0_DEV_CNTRL1_MM 0x2f0040 +#define F1_DEV_CNTRL1_MM 0x2f0140 +#define F2_DEV_CNTRL1_MM 0x2f0240 +#define F3_DEV_CNTRL1_MM 0x2f0340 +#define F4_DEV_CNTRL1_MM 0x2f0440 + +/* Device Control #1 */ +#define F0_BAR0_MM 0x2f0010 +#define F1_BAR0_MM 0x2f0110 +#define F2_BAR0_MM 0x2f0210 +#define F3_BAR0_MM 0x2f0310 +#define F4_BAR0_MM 0x2f0410 /* ---------------------------------------------------------------------- */ /* DMA Controller registers */ @@ -395,6 +419,7 @@ #define AUD_RATE_ADJ4 0x3205e4 #define AUD_RATE_ADJ5 0x3205e8 #define AUD_APB_IN_RATE_ADJ 0x3205ec +#define AUD_I2SCNTL 0x3205ec #define AUD_PHASE_FIX_CTL 0x3205f0 #define AUD_PLL_PRESCALE 0x320600 #define AUD_PLL_DDS 0x320604 @@ -502,12 +527,6 @@ #define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream #define MO_GPHSTU_DMA 0x350008 // {64}RWp Host upstream -#define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter -#define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter -#define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control -#define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control -#define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control -#define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status #define MO_GPHSTU_CNTRL 0x380048 // Host upstream control #1 #define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2 #define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length @@ -518,6 +537,14 @@ #define MO_GPHST_MUX16 0x380064 // Host muxed 16-bit transfer parameters #define MO_GPHST_MODE 0x380068 // Host mode select +#define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter +#define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter +#define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control +#define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control +#define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control +#define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status +#define MO_GPHST_SOFT_RST 0x38C06C // Host software reset + /* ---------------------------------------------------------------------- */ /* RISC instructions */ @@ -555,11 +582,11 @@ /* ---------------------------------------------------------------------- */ /* various constants */ -#define SEL_BTSC 0x01 -#define SEL_EIAJ 0x02 -#define SEL_A2 0x04 +#define SEL_BTSC 0x01 +#define SEL_EIAJ 0x02 +#define SEL_A2 0x04 #define SEL_SAP 0x08 -#define SEL_NICAM 0x10 +#define SEL_NICAM 0x10 #define SEL_FMRADIO 0x20 // AUD_CTL @@ -599,12 +626,13 @@ #define EN_I2SIN_STR2DAC 0x00004000 #define EN_I2SIN_ENABLE 0x00008000 -#define EN_DMTRX_SUMDIFF 0x00000800 -#define EN_DMTRX_SUMR 0x00000880 -#define EN_DMTRX_LR 0x00000900 -#define EN_DMTRX_MONO 0x00000980 +#define EN_DMTRX_SUMDIFF (0 << 7) +#define EN_DMTRX_SUMR (1 << 7) +#define EN_DMTRX_LR (2 << 7) +#define EN_DMTRX_MONO (3 << 7) +#define EN_DMTRX_BYPASS (1 << 11) -// Video +// Video #define VID_CAPTURE_CONTROL 0x310180 #define CX23880_CAP_CTL_CAPTURE_VBI_ODD (1<<3) @@ -616,10 +644,10 @@ #define VideoInputMux1 0x1 #define VideoInputMux2 0x2 #define VideoInputMux3 0x3 -#define VideoInputTuner 0x0 -#define VideoInputComposite 0x1 +#define VideoInputTuner 0x0 +#define VideoInputComposite 0x1 #define VideoInputSVideo 0x2 -#define VideoInputOther 0x3 +#define VideoInputOther 0x3 #define Xtal0 0x1 #define Xtal1 0x2 @@ -630,12 +658,12 @@ #define VideoFormatNTSCJapan 0x2 #define VideoFormatNTSC443 0x3 #define VideoFormatPAL 0x4 -#define VideoFormatPALB 0x4 -#define VideoFormatPALD 0x4 -#define VideoFormatPALG 0x4 -#define VideoFormatPALH 0x4 -#define VideoFormatPALI 0x4 -#define VideoFormatPALBDGHI 0x4 +#define VideoFormatPALB 0x4 +#define VideoFormatPALD 0x4 +#define VideoFormatPALG 0x4 +#define VideoFormatPALH 0x4 +#define VideoFormatPALI 0x4 +#define VideoFormatPALBDGHI 0x4 #define VideoFormatPALM 0x5 #define VideoFormatPALN 0x6 #define VideoFormatPALNC 0x7 @@ -647,12 +675,12 @@ #define VideoFormatNTSCJapan27MHz 0x12 #define VideoFormatNTSC44327MHz 0x13 #define VideoFormatPAL27MHz 0x14 -#define VideoFormatPALB27MHz 0x14 -#define VideoFormatPALD27MHz 0x14 -#define VideoFormatPALG27MHz 0x14 -#define VideoFormatPALH27MHz 0x14 -#define VideoFormatPALI27MHz 0x14 -#define VideoFormatPALBDGHI27MHz 0x14 +#define VideoFormatPALB27MHz 0x14 +#define VideoFormatPALD27MHz 0x14 +#define VideoFormatPALG27MHz 0x14 +#define VideoFormatPALH27MHz 0x14 +#define VideoFormatPALI27MHz 0x14 +#define VideoFormatPALBDGHI27MHz 0x14 #define VideoFormatPALM27MHz 0x15 #define VideoFormatPALN27MHz 0x16 #define VideoFormatPALNC27MHz 0x17 @@ -700,13 +728,13 @@ #define ColorFormatGamma 0x1000 #define Interlaced 0x1 -#define NonInterlaced 0x0 +#define NonInterlaced 0x0 #define FieldEven 0x1 #define FieldOdd 0x0 -#define TGReadWriteMode 0x0 -#define TGEnableMode 0x1 +#define TGReadWriteMode 0x0 +#define TGEnableMode 0x1 #define DV_CbAlign 0x0 #define DV_Y0Align 0x1 @@ -731,8 +759,8 @@ #define CHANNEL_VIP_UP 0xA #define CHANNEL_HOST_DN 0xB #define CHANNEL_HOST_UP 0xC -#define CHANNEL_FIRST 0x1 -#define CHANNEL_LAST 0xC +#define CHANNEL_FIRST 0x1 +#define CHANNEL_LAST 0xC #define GP_COUNT_CONTROL_NONE 0x0 #define GP_COUNT_CONTROL_INC 0x1 @@ -759,15 +787,15 @@ #define DEFAULT_SAT_U_NTSC 0x7F #define DEFAULT_SAT_V_NTSC 0x5A -typedef enum -{ - SOURCE_TUNER = 0, - SOURCE_COMPOSITE, - SOURCE_SVIDEO, - SOURCE_OTHER1, - SOURCE_OTHER2, - SOURCE_COMPVIASVIDEO, - SOURCE_CCIR656 +typedef enum +{ + SOURCE_TUNER = 0, + SOURCE_COMPOSITE, + SOURCE_SVIDEO, + SOURCE_OTHER1, + SOURCE_OTHER2, + SOURCE_COMPVIASVIDEO, + SOURCE_CCIR656 } VIDEOSOURCETYPE; #endif /* _CX88_REG_H_ */